GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/reg_file/reg_operations_pkg.vhd Lines: 25 59 42.4 %
Date: 2021-06-12 04:12:08 Branches: 115 315 36.5 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library common;
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use common.addr_pkg.all;
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use common.types_pkg.all;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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package reg_operations_pkg is
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  -- Default bus handle that can be used to simplify calls.
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  constant regs_bus_master : bus_master_t := new_bus(
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    data_length => 32, address_length => 32, logger => get_logger("regs_bus_master"));
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  -- Some common register operations.
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  procedure read_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : out reg_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure read_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : out integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure check_reg_equal(
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    signal net : inout network_t;
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    reg_index : in natural;
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    expected : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure check_reg_equal(
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    signal net : inout network_t;
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    reg_index : in natural;
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    expected : in reg_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure check_reg_equal_bits(
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    signal net : inout network_t;
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    reg_index : in natural;
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    expected_bits : in natural_vec_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure check_reg_equal_bit(
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    signal net : inout network_t;
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    reg_index : in natural;
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    expected_bit : in natural;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure write_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in reg_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure write_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in unsigned(reg_width - 1 downto 0);
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure write_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure write_reg_bits(
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    signal net : inout network_t;
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    reg_index : in natural;
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    bits : in natural_vec_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure write_reg_bit(
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    signal net : inout network_t;
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    reg_index : in natural;
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    bit_index : in natural;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure wait_until_reg_equals(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in reg_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master;
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    timeout : delay_length := delay_length'high;
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    message : string := "");
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  procedure wait_until_reg_equals(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master;
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    timeout : delay_length := delay_length'high;
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    message : string := ""
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  );
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  procedure wait_until_reg_equals_bits(
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    signal net : inout network_t;
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    reg_index : in natural;
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    bits : in natural_vec_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master;
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    timeout : delay_length := delay_length'high;
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    message : string := "");
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  procedure wait_until_reg_equals_bit(
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    signal net : inout network_t;
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    reg_index : in natural;
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    bit : in natural;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master;
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    timeout : delay_length := delay_length'high;
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    message : string := "");
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end;
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package body reg_operations_pkg is
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  procedure read_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : out reg_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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11682
    variable address : addr_t;
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  begin
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    address := base_address or to_unsigned(4 * reg_index, address'length);
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2130
    read_bus(net, bus_handle, std_logic_vector(address), value);
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  end procedure;
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  procedure read_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : out integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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    variable slv_value : reg_t;
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  begin
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    read_reg(net, reg_index, slv_value, base_address, bus_handle);
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    value := to_integer(unsigned(slv_value));
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  end procedure;
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  procedure check_reg_equal(
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    signal net : inout network_t;
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    reg_index : in natural;
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    expected : in reg_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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    variable got : reg_t;
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  begin
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    read_reg(net, reg_index, got, base_address, bus_handle);
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    check_equal(got, expected, "base_address: " & to_string(base_address) & " reg_index: " & to_string(reg_index), line_num => 184, file_name => "reg_operations_pkg.vhd");
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  end procedure;
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  procedure check_reg_equal(
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    signal net : inout network_t;
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    reg_index : in natural;
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    expected : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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    variable got : integer;
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  begin
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    read_reg(net, reg_index, got, base_address, bus_handle);
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    check_equal(got, expected, "base_address: " & to_string(base_address) & " reg_index: " & to_string(reg_index), line_num => 196, file_name => "reg_operations_pkg.vhd");
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  end procedure;
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  procedure check_reg_equal_bits(
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    signal net : inout network_t;
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    reg_index : in natural;
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    expected_bits : in natural_vec_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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    variable expected : reg_t := (others => '0');
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  begin
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    -- Check that reg has value with only the bits in "expected_bits" set.
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    for vec_index in expected_bits'range loop
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      expected(expected_bits(vec_index)) := '1';
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    end loop;
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    check_reg_equal(net, reg_index, expected, base_address, bus_handle);
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  end procedure;
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  procedure check_reg_equal_bit(
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    signal net : inout network_t;
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    reg_index : in natural;
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    expected_bit : in natural;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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  begin
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    -- Check that reg has value with only the "expected_bit" bit set.
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    check_reg_equal_bits(net, reg_index, (0 => expected_bit), base_address, bus_handle);
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  end procedure;
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  procedure write_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in reg_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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    variable address : addr_t;
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  begin
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      address := base_address or to_unsigned(4 * reg_index, address'length);
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      write_bus(net, bus_handle, std_logic_vector(address), value);
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    end procedure;
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  procedure write_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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  begin
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    write_reg(net, reg_index, std_logic_vector(to_signed(value, reg_width)), base_address, bus_handle);
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  end procedure;
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  procedure write_reg(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in unsigned(reg_width - 1 downto 0);
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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  begin
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    write_reg(net, reg_index, std_logic_vector(value), base_address, bus_handle);
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  end procedure;
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  procedure write_reg_bits(
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    signal net : inout network_t;
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    reg_index : in natural;
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    bits : in natural_vec_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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    variable data : reg_t := (others => '0');
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  begin
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    -- Write with only the bits listed in "bits" asserted.
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    for vec_index in bits'range loop
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      data(bits(vec_index)) := '1';
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    end loop;
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    write_reg(net, reg_index, data, base_address, bus_handle);
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  end procedure;
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  procedure write_reg_bit(
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    signal net : inout network_t;
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    reg_index : in natural;
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    bit_index : in natural;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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  begin
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    -- Write with only the bit "bit_index" asserted.
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    write_reg_bits(net, reg_index, (0 => bit_index), base_address, bus_handle);
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  end procedure;
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  procedure wait_until_reg_equals(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in reg_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master;
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    timeout : delay_length := delay_length'high;
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    message : string := "") is
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    constant address : addr_t := base_address or to_unsigned(4 * reg_index, addr_t'length);
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  begin
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    wait_until_read_equals(
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      net=>net,
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      bus_handle=>bus_handle,
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      addr=>std_logic_vector(address),
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      value=>value,
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      timeout=>timeout,
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      msg=>message
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    );
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  end procedure;
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  procedure wait_until_reg_equals(
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    signal net : inout network_t;
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    reg_index : in natural;
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    value : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master;
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    timeout : delay_length := delay_length'high;
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    message : string := ""
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  ) is
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  begin
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    wait_until_reg_equals(
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      net=>net,
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      reg_index=>reg_index,
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      value=>std_logic_vector(to_unsigned(value, reg_width)),
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      base_address=>base_address,
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      bus_handle=>bus_handle,
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      timeout=>timeout,
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      message=>message
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    );
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  end procedure;
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  procedure wait_until_reg_equals_bits(
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    signal net : inout network_t;
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    reg_index : in natural;
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    bits : in natural_vec_t;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master;
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    timeout : delay_length := delay_length'high;
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    message : string := "") is
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    constant start_time : time := now;
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    variable read_data : reg_t;
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    variable test_ok : boolean;
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  begin
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    -- Wait until all the bits listed in "bits" are read as true.
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    while now - start_time <= timeout loop
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      read_reg(net, reg_index, read_data, base_address, bus_handle);
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      test_ok := true;
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      for vector_index in bits'range loop
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        test_ok := test_ok and (read_data(bits(vector_index)) = '1');
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      end loop;
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      if test_ok then
347
        return;
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      end if;
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    end loop;
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    assert false report "Timeout! " & message;
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  end procedure;
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  procedure wait_until_reg_equals_bit(
355
    signal net : inout network_t;
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    reg_index : in natural;
357
    bit : in natural;
358
    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master;
360
    timeout : delay_length := delay_length'high;
361
    message : string := "") is
362
  begin
363
    -- Wait until the bit in "bit" is read as true.
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22
    wait_until_reg_equals_bits(net, reg_index, (0 => bit), base_address, bus_handle, timeout, message);
365
  end procedure;
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end;