GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/reg_file/tb_interrupt_register.vhd Lines: 53 53 100.0 %
Date: 2021-06-12 04:12:08 Branches: 178 244 73.0 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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entity tb_interrupt_register is
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  generic (
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_interrupt_register is
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  signal clk : std_logic := '0';
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  signal sources, mask, clear, status : reg_t := (others => '0');
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  signal trigger : std_logic := '0';
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begin
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  test_runner_watchdog(runner, 2 ms);
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  clk <= not clk after 2 ns;
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  ------------------------------------------------------------------------------
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  main : process
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    procedure wait_one_cycle is
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    begin
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      wait until rising_edge(clk);
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    end procedure;
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    procedure wait_a_while is
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    begin
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      wait until rising_edge(clk);
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      wait until rising_edge(clk);
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    end procedure;
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    procedure check_status(high_bits : integer_vector) is
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      variable expected : reg_t := (others => '0');
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    begin
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      for list_idx in high_bits'range loop
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        expected(high_bits(list_idx)) := '1';
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      end loop;
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      check_equal(status, expected, line_num => 57, file_name => "tb_interrupt_register.vhd");
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    end procedure;
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    procedure check_trigger is
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    begin
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      check_equal(trigger, '1', line_num => 62, file_name => "tb_interrupt_register.vhd");
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    end procedure;
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    procedure check_no_trigger is
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      variable expected : reg_t := (others => '0');
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    begin
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      check_equal(trigger, '0', line_num => 68, file_name => "tb_interrupt_register.vhd");
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    sources <= (0 => '1', 1 => '1', 2 => '1', others => '0');
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    wait_a_while;
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    check_status((0, 1, 2));
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    check_no_trigger;
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    -- Source bit and mask bit being high for (at least) one cycle should trigger
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    mask(0) <= '1';
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    wait_one_cycle;
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    sources(0) <= '0';
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    wait_a_while;
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    check_status((0, 1, 2));
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    check_trigger;
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    if run("test_clear_register_wipes_trigger") then
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      clear(0) <= '1';
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      wait_one_cycle;
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      clear <= (others => '0');
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      wait_one_cycle;
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      -- Both status bit and trigger are cleared
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      check_status((1, 2));
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      check_no_trigger;
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    elsif run("test_changing_mask_wipes_trigger") then
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      mask(0) <= '0';
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      wait_a_while;
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      -- Trigger is cleared but status remains
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      check_status((0, 1, 2));
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      check_no_trigger;
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    end if;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.interrupt_register
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    port map (
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      clk => clk,
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      sources => sources,
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      mask => mask,
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      clear => clear,
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      status => status,
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      trigger => trigger
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    );
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end architecture;