GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/resync/resync_level_on_signal.vhd Lines: 8 8 100.0 %
Date: 2021-06-12 04:12:08 Branches: 14 18 77.8 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Sample a bit from one clock domain to another.
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--
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-- This modules does not utilize any meta stability protection.
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-- It is up to the user to ensure that data_in is stable when sample_value is asserted.
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--
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-- Note that unlike e.g. resync_level, it is safe to drive the input of this entity with LUTs
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-- as well as FFs.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library common;
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use common.attribute_pkg.all;
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entity resync_level_on_signal is
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  generic (
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    -- Initial value for the ouput that will be set until the first input value has propagated
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    -- and been sampled.
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    default_value : std_logic := '0'
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  );
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  port (
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   data_in : in std_logic;
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   clk_out : in std_logic;
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   sample_value : in std_logic;
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   data_out : out std_logic := default_value
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  );
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end entity;
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architecture a of resync_level_on_signal is
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  signal data_in_int : std_logic;
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  attribute dont_touch of data_in_int : signal is "true"; -- Keep net so that we can apply constraint
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begin
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  data_in_int <= data_in;
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  ------------------------------------------------------------------------------
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  main : process
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  begin
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    wait until rising_edge(clk_out);
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    if sample_value then
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      data_out <= data_in_int;
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    end if;
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  end process;
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end architecture;