GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/resync/resync_slv_level.vhd Lines: 5 5 100.0 %
Date: 2021-06-12 04:12:08 Branches: 4 5 80.0 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Resync a vector from one clock domain to another. This simple vector resync mechanism does not
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-- guarantee any coherency between the bits. There might be a large skew between different bits.
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--
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-- See resync_level header for details about constraining.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity resync_slv_level is
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  generic (
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    width : positive;
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    -- Enable or disable a register on the input side before the async_reg flip-flip chain.
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    -- Must be used if the input can contain glitches. See resync_slv header for more details.
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    -- The 'clk_in' port must be assigned if this generic is set to 'true'.
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    enable_input_register : boolean;
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    -- Initial value for the ouput that will be set for a few cycles before the first input
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    -- value has propagated.
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    default_value : std_logic_vector(width - 1 downto 0) := (others => '0')
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  );
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  port (
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    clk_in : in std_logic := '-';
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    data_in : in std_logic_vector(default_value'range);
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    clk_out : in std_logic;
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    data_out : out std_logic_vector(default_value'range) := default_value
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  );
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end entity;
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architecture a of resync_slv_level is
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begin
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  ------------------------------------------------------------------------------
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  resync_gen : for i in data_in'range generate
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  begin
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    ------------------------------------------------------------------------------
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    resync_level_inst : entity work.resync_level
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      generic map (
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        enable_input_register => enable_input_register,
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        default_value => default_value(i)
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      )
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      port map (
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        clk_in => clk_in,
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        data_in => data_in(i),
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        clk_out => clk_out,
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        data_out => data_out(i)
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      );
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  end generate;
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end architecture;