GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/resync/tb_resync_counter.vhd Lines: 31 31 100.0 %
Date: 2021-06-12 04:12:08 Branches: 113 170 66.5 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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library common;
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use common.types_pkg.all;
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entity tb_resync_counter is
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  generic (
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    runner_cfg      : string;
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    pipeline_output : boolean
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    );
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end entity;
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architecture tb of tb_resync_counter is
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  constant clk_in_period   : time    := 3.3 ns;
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  constant clk_out_period  : time    := 4 ns;
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  constant max_resync_time : time :=
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    clk_in_period +
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    2*clk_out_period +
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    to_int(pipeline_output) * clk_out_period;
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  signal clk_in                  : std_logic                      := '1';
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  signal clk_out                 : std_logic                      := '0';
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  signal counter_in, counter_out : unsigned(8 - 1 downto 0) := (others => '0');
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  constant counter_max : integer := 2 ** counter_in'length - 1;
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begin
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  test_runner_watchdog(runner, 10 ms);
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165307
  clk_in  <= not clk_in  after clk_in_period/2;
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  clk_out <= not clk_out after clk_out_period/2;
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  ------------------------------------------------------------------------------
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  main : process
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    procedure apply_and_check(value : integer) is
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    begin
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      wait until rising_edge(clk_in);
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      counter_in <= to_unsigned(value, counter_in'length);
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      wait until counter_out'event for max_resync_time;
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      wait until rising_edge(clk_out);
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      check_equal(counter_out, value, line_num => 53, file_name => "tb_resync_counter.vhd");
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      wait until counter_out'event for 40*clk_out_period;
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      assert not counter_out'event;
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    loop_twice_to_wrap_counter : for i in 1 to 2 loop
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      count_up : for value in 0 to counter_max loop
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        apply_and_check(value);
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      end loop;
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    end loop;
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    count_down : for value in counter_max downto 0 loop
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      apply_and_check(value);
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    end loop;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.resync_counter
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    generic map (
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      width => counter_in'length,
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      pipeline_output => pipeline_output)
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    port map (
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      clk_in     => clk_in,
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      counter_in => counter_in,
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      clk_out     => clk_out,
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      counter_out => counter_out);
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end architecture;