GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/resync/tb_resync_cycles.vhd Lines: 51 51 100.0 %
Date: 2021-06-12 04:12:08 Branches: 133 194 68.6 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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library common;
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use common.types_pkg.all;
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30976
entity tb_resync_cycles is
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  generic (
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    output_clock_is_faster : boolean := false;
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    output_clock_is_slower : boolean := false;
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    active_high : boolean;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_resync_cycles is
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  constant counter_width : integer := 3;
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  constant clock_period_fast : time := 2 ns;
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  constant clock_period_medium : time := 5 ns;
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  constant clock_period_slow : time := 10 ns;
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  constant active_level : std_logic := to_sl(active_high);
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  function clk_out_period return time is
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  begin
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30934
    if output_clock_is_faster then
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21130
      return clock_period_fast;
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9804
    elsif output_clock_is_slower then
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      return clock_period_slow;
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    else
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      return clock_period_medium;
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    end if;
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  end function;
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  signal clk_in, clk_out : std_logic := '0';
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  signal data_in, data_out : std_logic := not active_level;
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  signal num_data_out : integer := 0;
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  signal reset_reference_counter : boolean := false;
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begin
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  test_runner_watchdog(runner, 100 us);
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  clk_in <= not clk_in after clock_period_medium / 2;
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30934
  clk_out <= not clk_out after clk_out_period / 2;
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  ------------------------------------------------------------------------------
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  main : process
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38944
    procedure test(num_cycles : integer) is
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      variable start_time : time;
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    begin
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      wait until rising_edge(clk_out);
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      reset_reference_counter <= true;
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      wait until rising_edge(clk_out);
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      reset_reference_counter <= false;
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      start_time := now;
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      for i in 1 to num_cycles loop
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        wait until rising_edge(clk_in);
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        data_in <= active_level;
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      end loop;
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      wait until rising_edge(clk_in);
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      data_in <= not active_level;
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      wait until rising_edge(clk_out) and
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        ((now - start_time) > ((num_cycles + 5) * clock_period_slow));
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39290
      check_equal(num_data_out, num_cycles, line_num => 83, file_name => "tb_resync_cycles.vhd");
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    wait until rising_edge(clk_in);
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    if output_clock_is_slower then
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      -- The resync may fail only after 2**counter_width input cycles
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      for test_num in 1 to 10 loop
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        test(2**counter_width);
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        test(2**counter_width);
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      end loop;
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    else
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      for test_num in 1 to 10 loop
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        test(100);
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      end loop;
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    end if;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  output : process
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  begin
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    wait until rising_edge(clk_out);
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    if reset_reference_counter then
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      num_data_out <= 0;
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    elsif data_out = active_level then
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      num_data_out <= num_data_out + 1;
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    end if;
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.resync_cycles
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    generic map (
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      counter_width => counter_width,
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      active_level => active_level
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    )
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    port map (
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      clk_in => clk_in,
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      data_in => data_in,
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      clk_out => clk_out,
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      data_out => data_out);
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end architecture;