GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/resync/tb_resync_pulse.vhd Lines: 37 37 100.0 %
Date: 2021-06-12 04:12:08 Branches: 92 141 65.2 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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entity tb_resync_pulse is
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  generic (
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    output_clock_is_faster : boolean := false;
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    output_clock_is_slower : boolean := false;
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    input_pulse_overload : boolean := false;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_resync_pulse is
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  constant clock_period_fast : time := 2 ns;
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  constant clock_period_medium : time := 5 ns;
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  constant clock_period_slow : time := 10 ns;
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  constant sleep_between_pulses : time := 10 * clock_period_slow;
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  signal clk_in, clk_out : std_logic := '0';
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  signal pulse_in, pulse_out : std_logic;
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  signal num_pulses_out : integer := 0;
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begin
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  test_runner_watchdog(runner, 10 ms);
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  clk_in <= not clk_in after clock_period_medium / 2;
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  clock_out_gen : if output_clock_is_faster generate
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    clk_out <= not clk_out after clock_period_fast / 2;
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  elsif output_clock_is_slower generate
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    clk_out <= not clk_out after clock_period_slow / 2;
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  else generate
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    clk_out <= transport clk_in after clock_period_medium / 5;
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  end generate;
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  ------------------------------------------------------------------------------
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  main : process
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    procedure test_pulse(expected_num_pulses : integer) is
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    begin
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      wait until rising_edge(clk_in);
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      pulse_in <= '1';
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      wait until rising_edge(clk_in);
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      pulse_in <= '0';
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      if input_pulse_overload then
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        -- Send another pulse
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        wait until rising_edge(clk_in);
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        pulse_in <= '1';
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        wait until rising_edge(clk_in);
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        pulse_in <= '0';
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      end if;
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      wait for sleep_between_pulses;
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      check_equal(num_pulses_out, expected_num_pulses, line_num => 71, file_name => "tb_resync_pulse.vhd");
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    for i in 1 to 100 loop
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      -- In the case of input_pulse_overload we will send more than one input pulse per call to test_pulse().
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      -- But the input gating will make sure that only one pulse arrives on the output, so expected_num_pulses is still i.
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      test_pulse(i);
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    end loop;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  output : process
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  begin
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    wait until pulse_out = '1' and rising_edge(clk_out);
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    num_pulses_out <= num_pulses_out + 1;
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.resync_pulse
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    generic map (
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      assert_false_on_pulse_overload => not input_pulse_overload
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    )
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    port map (
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      clk_in => clk_in,
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      pulse_in => pulse_in,
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      clk_out => clk_out,
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      pulse_out => pulse_out);
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end architecture;