GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/resync/tb_resync_slv_level.vhd Lines: 50 50 100.0 %
Date: 2021-06-12 04:12:08 Branches: 130 192 67.7 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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1110
entity tb_resync_slv_level is
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  generic (
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    test_coherent : boolean;
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    output_clock_is_faster : boolean;
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    enable_input_register : boolean;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_resync_slv_level is
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  constant clock_period_fast : time := 2 ns;
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  constant clock_period_medium : time := 10 ns;
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  constant clock_period_slow : time := 10 ns;
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  function clk_out_period return time is
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  begin
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    if output_clock_is_faster then
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      return clock_period_fast;
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    else
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      return clock_period_slow;
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    end if;
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  end function;
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  constant one : std_logic_vector(16 - 1 downto 0) := x"1111";
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  constant two : std_logic_vector(one'range) := x"2222";
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  signal clk_in, clk_out : std_logic := '0';
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  signal data_in, data_out : std_logic_vector(one'range) := one;
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begin
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  test_runner_watchdog(runner, 10 ms);
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  clk_out <= not clk_out after clk_out_period / 2;
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  clk_in <= not clk_in after clock_period_medium / 2;
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2
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  ------------------------------------------------------------------------------
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  main : process
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    procedure wait_cycles(signal clk : std_logic; num_cycles : in integer) is
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    begin
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      for i in 0 to num_cycles-1 loop
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        wait until rising_edge(clk);
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      end loop;
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    end procedure;
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    procedure wait_for_input_value_to_propagate is
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      variable clk_in_wait_count, clk_out_wait_count : natural := 0;
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    begin
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      -- Wait to assign input value in tb
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      clk_in_wait_count := 1;
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      -- Two registers
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      clk_out_wait_count := 2;
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      if test_coherent then
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        clk_in_wait_count := clk_in_wait_count + 3;
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      end if;
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      if enable_input_register then
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        clk_in_wait_count := clk_in_wait_count + 1;
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      end if;
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      wait_cycles(clk_in, clk_in_wait_count);
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      wait_cycles(clk_out, clk_out_wait_count);
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    -- Default value
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    check_equal(data_out, one, line_num => 88, file_name => "tb_resync_slv_level.vhd");
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    wait until rising_edge(clk_out);
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    check_equal(data_out, one, line_num => 91, file_name => "tb_resync_slv_level.vhd");
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    wait_cycles(clk_out, 40);
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    check_equal(data_out, one, line_num => 94, file_name => "tb_resync_slv_level.vhd");
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    data_in <= two;
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    wait_for_input_value_to_propagate;
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    check_equal(data_out, two, line_num => 98, file_name => "tb_resync_slv_level.vhd");
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    wait_cycles(clk_out, 40);
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    check_equal(data_out, two, line_num => 101, file_name => "tb_resync_slv_level.vhd");
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  assert_output_always_valid_value : process
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  begin
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    wait until rising_edge(clk_out);
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    assert data_out = one or data_out = two;
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  end process;
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  ------------------------------------------------------------------------------
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  choose_dut : if test_coherent generate
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    dut : entity work.resync_slv_level_coherent
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      generic map (
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        width => data_in'length,
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        default_value => one
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      )
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      port map (
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        clk_in => clk_in,
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        data_in => data_in,
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        clk_out => clk_out,
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        data_out => data_out
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      );
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  else generate
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    dut : entity work.resync_slv_level
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      generic map (
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        width => data_in'length,
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        enable_input_register => enable_input_register,
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        default_value => one
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      )
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      port map (
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        clk_in => clk_in,
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        data_in => data_in,
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        clk_out => clk_out,
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        data_out => data_out
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      );
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  end generate;
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end architecture;