GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/resync/tb_resync_slv_level_on_signal.vhd Lines: 32 32 100.0 %
Date: 2021-06-12 04:12:08 Branches: 107 158 67.7 %

Line Branch Exec Source
1
6
-- -------------------------------------------------------------------------------------------------
2
-- Copyright (c) Lukas Vik. All rights reserved.
3
--
4
-- This file is part of the tsfpga project.
5
-- https://tsfpga.com
6
-- https://gitlab.com/tsfpga/tsfpga
7
-- -------------------------------------------------------------------------------------------------
8
9
library ieee;
10
use ieee.std_logic_1164.all;
11
use ieee.numeric_std.all;
12
13
library vunit_lib;
14
context vunit_lib.vunit_context;
15
16
17













10
entity tb_resync_slv_level_on_signal is
18
  generic (
19
    runner_cfg : string
20
  );
21
end entity;
22
23
architecture tb of tb_resync_slv_level_on_signal is
24
1
  signal clk_out : std_logic := '0';
25
65
  signal data_in, data_out : std_logic_vector(16-1 downto 0) := (others => '0');
26
2
  signal sample_value : std_logic := '0';
27
begin
28
29

24
  test_runner_watchdog(runner, 10 ms);
30
167
  clk_out <= not clk_out after 2 ns;
31
1
32
1
33


34
  ------------------------------------------------------------------------------
34
1
  main : process
35


406
    procedure wait_cycles(signal clk : std_logic; num_cycles : in integer) is
36
    begin
37
2
      for i in 0 to num_cycles-1 loop
38







592
        wait until rising_edge(clk);
39
      end loop;
40
    end procedure;
41
17
    constant zero : std_logic_vector(data_in'range) := (others => '0');
42
21
    constant value : std_logic_vector(data_in'range) := x"BAAD";
43
  begin
44
3
    test_runner_setup(runner, runner_cfg);
45
46
    -- Module functionality is very simple. This is basically a connectivity test.
47
48

3
    wait until rising_edge(clk_out);
49
2
    check_equal(data_out, zero, line_num => 49, file_name => "tb_resync_slv_level_on_signal.vhd");
50

17
    data_in <= value;
51
52
82
    wait_cycles(clk_out, 40);
53
2
    check_equal(data_out, zero, line_num => 53, file_name => "tb_resync_slv_level_on_signal.vhd");
54

1
    sample_value <= '1';
55
56

4
    wait until rising_edge(clk_out);
57

1
    sample_value <= '0';
58

17
    data_in <= zero;
59
60

4
    wait until rising_edge(clk_out);
61
2
    check_equal(data_out, value, line_num => 61, file_name => "tb_resync_slv_level_on_signal.vhd");
62
63
82
    wait_cycles(clk_out, 40);
64
2
    check_equal(data_out, value, line_num => 64, file_name => "tb_resync_slv_level_on_signal.vhd");
65
66
20
    test_runner_cleanup(runner);
67
  end process;
68
69
70
  ------------------------------------------------------------------------------
71

17
  dut : entity work.resync_slv_level_on_signal
72
    generic map (
73
      width => data_in'length
74
    )
75
    port map (
76
      data_in => data_in,
77
78
      clk_out => clk_out,
79
      sample_value => sample_value,
80
      data_out => data_out
81
    );
82
83
end architecture;