tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/handshake_splitter.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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Branches: 5 10 50.0%

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1 6 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Note that this block can break the AXI-Stream protocol. If one of the outputs
9 -- lowers ready, that will lower valid for the other output. Use only in situations
10 -- that can handle this.
11 -- -------------------------------------------------------------------------------------------------
12
13 library ieee;
14 use ieee.std_logic_1164.all;
15
16
17
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3972 entity handshake_splitter is
18 port (
19 clk : in std_logic;
20 --
21 input_ready : out std_logic;
22 input_valid : in std_logic;
23 --
24 output0_ready : in std_logic;
25 output0_valid : out std_logic := '0';
26 --
27 output1_ready : in std_logic;
28 output1_valid : out std_logic := '0'
29 );
30 end entity;
31
32 2 architecture a of handshake_splitter is
33 begin
34
35 6613 input_ready <= output0_ready and output1_ready;
36
37
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2649 output0_valid <= input_valid and output1_ready;
38
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2696 output1_valid <= input_valid and output0_ready;
39
40 end architecture;
41