tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/reg_file/interrupt_register.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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Branches: 8 11 72.7%

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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library reg_file;
14 use reg_file.reg_file_pkg.all;
15
16
17
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584 entity interrupt_register is
18 port (
19 clk : in std_logic;
20
21 sources : in reg_t := (others => '0');
22 mask : in reg_t := (others => '1');
23 clear : in reg_t := (others => '0');
24
25 status : out reg_t := (others => '0');
26 trigger : out std_logic := '0'
27 );
28 end entity;
29
30 4 architecture a of interrupt_register is
31 begin
32
33 2 main : process
34 130 variable status_next : reg_t := (others => '0');
35 begin
36 56 wait until rising_edge(clk);
37
38 14 for idx in sources'range loop
39 448 if clear(idx) then
40 1 status_next(idx) := '0';
41 447 elsif sources(idx) then
42 34 status_next(idx) := '1';
43 else
44 448 status_next(idx) := status(idx);
45 end if;
46 end loop;
47
48 14 trigger <= or (status_next and mask);
49
50 478 status <= status_next;
51 end process;
52
53 end architecture;
54