tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/reg_file/reg_operations_pkg.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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Branches: 179 323 55.4%

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2428 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Various helper functions for reading/writing/checking registers.
9 --
10 -- There is an intentional asymmetry in the default value for 'other_bits_value' between
11 -- 'check_reg_equal_bit(s)' and 'wait_until_reg_equals_bit(s)'.
12 -- For the former it is '0' while it is '-' for the latter.
13 -- This is based on the philosophy that a false positive is better than a hidden error.
14 -- False positives, when discovered, can be worked around by e.g. changing the default value.
15 --
16 -- Consider the example of reading an error status register. When we want to check that the expected
17 -- error bit has been set, we would like to be informed if any other error has occured. This would
18 -- not occur unless 'other_bits_value' value to 'check_reg_equal_bit(s)' is '0'.
19 -- Consider the situation where we are 'waiting' for a certain error bit to be asserted in a test,
20 -- but ten other errors occur. In this scenario we would like the 'wait' to end, and for the
21 -- errors to have consequences. This would not occur unless 'other_bits_value' value to
22 -- 'wait_until_reg_equals_bit(s)' is '-'
23 -- -------------------------------------------------------------------------------------------------
24
25 library ieee;
26 use ieee.std_logic_1164.all;
27 use ieee.numeric_std.all;
28
29 library vunit_lib;
30 context vunit_lib.vunit_context;
31 context vunit_lib.vc_context;
32
33 library common;
34 use common.addr_pkg.all;
35 use common.types_pkg.all;
36
37 library reg_file;
38 use reg_file.reg_file_pkg.all;
39
40
41 package reg_operations_pkg is
42
43 -- Default bus handle that can be used to simplify calls.
44 173 constant regs_bus_master : bus_master_t := new_bus(
45 data_length => 32,
46 address_length => 32,
47 logger => get_logger("regs_bus_master")
48 );
49
50 -- Some common register operations.
51
52 procedure read_reg(
53 signal net : inout network_t;
54 reg_index : in natural;
55 value : out reg_t;
56 base_address : in addr_t := (others => '0');
57 bus_handle : in bus_master_t := regs_bus_master
58 );
59
60 procedure read_reg(
61 signal net : inout network_t;
62 reg_index : in natural;
63 value : out integer;
64 base_address : in addr_t := (others => '0');
65 bus_handle : in bus_master_t := regs_bus_master
66 );
67
68 procedure check_reg_equal(
69 signal net : inout network_t;
70 reg_index : in natural;
71 value : in integer;
72 base_address : in addr_t := (others => '0');
73 bus_handle : in bus_master_t := regs_bus_master;
74 message : in string := ""
75 );
76
77 procedure check_reg_equal(
78 signal net : inout network_t;
79 reg_index : in natural;
80 value : in reg_t;
81 base_address : in addr_t := (others => '0');
82 bus_handle : in bus_master_t := regs_bus_master;
83 message : in string := ""
84 );
85
86 procedure check_reg_equal_bits(
87 signal net : inout network_t;
88 reg_index : in natural;
89 bit_indexes : in natural_vec_t;
90 values : in std_logic_vector;
91 other_bits_value : in std_logic := '0';
92 base_address : in addr_t := (others => '0');
93 bus_handle : in bus_master_t := regs_bus_master;
94 message : in string := ""
95 );
96
97 procedure check_reg_equal_bit(
98 signal net : inout network_t;
99 reg_index : in natural;
100 bit_index : in natural;
101 value : in std_logic;
102 other_bits_value : in std_logic := '0';
103 base_address : in addr_t := (others => '0');
104 bus_handle : in bus_master_t := regs_bus_master;
105 message : in string := ""
106 );
107
108 procedure wait_until_reg_equals(
109 signal net : inout network_t;
110 reg_index : in natural;
111 value : in reg_t;
112 base_address : in addr_t := (others => '0');
113 bus_handle : in bus_master_t := regs_bus_master;
114 timeout : delay_length := max_timeout;
115 message : string := ""
116 );
117
118 procedure wait_until_reg_equals(
119 signal net : inout network_t;
120 reg_index : in natural;
121 value : in integer;
122 base_address : in addr_t := (others => '0');
123 bus_handle : in bus_master_t := regs_bus_master;
124 timeout : delay_length := max_timeout;
125 message : string := ""
126 );
127
128 procedure wait_until_reg_equals_bits(
129 signal net : inout network_t;
130 reg_index : in natural;
131 bit_indexes : in natural_vec_t;
132 values : in std_logic_vector;
133 other_bits_value : in std_logic := '-';
134 base_address : in addr_t := (others => '0');
135 bus_handle : in bus_master_t := regs_bus_master;
136 timeout : delay_length := max_timeout;
137 message : string := ""
138 );
139
140 procedure wait_until_reg_equals_bit(
141 signal net : inout network_t;
142 reg_index : in natural;
143 bit_index : in natural;
144 value : in std_logic;
145 other_bits_value : in std_logic := '-';
146 base_address : in addr_t := (others => '0');
147 bus_handle : in bus_master_t := regs_bus_master;
148 timeout : delay_length := max_timeout;
149 message : string := ""
150 );
151
152 procedure write_reg(
153 signal net : inout network_t;
154 reg_index : in natural;
155 value : in reg_t;
156 base_address : in addr_t := (others => '0');
157 bus_handle : in bus_master_t := regs_bus_master
158 );
159
160 procedure write_reg(
161 signal net : inout network_t;
162 reg_index : in natural;
163 value : in unsigned(reg_width - 1 downto 0);
164 base_address : in addr_t := (others => '0');
165 bus_handle : in bus_master_t := regs_bus_master
166 );
167
168 procedure write_reg(
169 signal net : inout network_t;
170 reg_index : in natural;
171 value : in integer;
172 base_address : in addr_t := (others => '0');
173 bus_handle : in bus_master_t := regs_bus_master
174 );
175
176 procedure write_reg_bits(
177 signal net : inout network_t;
178 reg_index : in natural;
179 bit_indexes : in natural_vec_t;
180 values : in std_logic_vector;
181 other_bits_value : in std_logic := '0';
182 base_address : in addr_t := (others => '0');
183 bus_handle : in bus_master_t := regs_bus_master
184 );
185
186 procedure write_reg_bit(
187 signal net : inout network_t;
188 reg_index : in natural;
189 bit_index : in natural;
190 value : in std_logic;
191 other_bits_value : in std_logic := '0';
192 base_address : in addr_t := (others => '0');
193 bus_handle : in bus_master_t := regs_bus_master
194 );
195
196 procedure read_modify_write_reg_bits(
197 signal net : inout network_t;
198 reg_index : in natural;
199 bit_indexes : in natural_vec_t;
200 values : in std_logic_vector;
201 base_address : in addr_t := (others => '0');
202 bus_handle : in bus_master_t := regs_bus_master
203 );
204
205 procedure read_modify_write_reg_bit(
206 signal net : inout network_t;
207 reg_index : in natural;
208 bit_index : in natural;
209 value : in std_logic;
210 base_address : in addr_t := (others => '0');
211 bus_handle : in bus_master_t := regs_bus_master
212 );
213
214 -- Internal helper function. Not meant to be used outside of this package.
215
216 function to_reg_value(
217 bit_indexes : natural_vec_t;
218 values : std_logic_vector;
219 previous_value : reg_t := (others => '0')
220 ) return reg_t;
221
222 end;
223
224 package body reg_operations_pkg is
225
226 function get_error_message(
227 reg_index : natural;
228 base_address : addr_t;
229 message : string
230 ) return string is
231
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151 constant result : string :=
232 "reg_index: " & to_string(reg_index) & ", base_address: " & to_string(base_address);
233 begin
234
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151 if message = "" then
235 151 return result;
236 end if;
237
238 return result & ", message: " & message;
239 end function;
240
241
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1866 procedure read_reg(
242 signal net : inout network_t;
243 reg_index : in natural;
244 value : out reg_t;
245 base_address : in addr_t := (others => '0');
246 bus_handle : in bus_master_t := regs_bus_master
247 ) is
248
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10230 variable address : addr_t;
249 begin
250
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310 address := base_address or to_unsigned(4 * reg_index, address'length);
251
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1866 read_bus(net, bus_handle, std_logic_vector(address), value);
252 end procedure;
253
254
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14 procedure read_reg(
255 signal net : inout network_t;
256 reg_index : in natural;
257 value : out integer;
258 base_address : in addr_t := (others => '0');
259 bus_handle : in bus_master_t := regs_bus_master
260 ) is
261
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66 variable slv_value : reg_t := (others => '0');
262 begin
263
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10 read_reg(net, reg_index, slv_value, base_address, bus_handle);
264 8 value := to_integer(signed(slv_value));
265 end procedure;
266
267
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2352 procedure check_reg_equal(
268 signal net : inout network_t;
269 reg_index : in natural;
270 value : in reg_t;
271 base_address : in addr_t := (others => '0');
272 bus_handle : in bus_master_t := regs_bus_master;
273 message : in string := ""
274 ) is
275
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9702 variable got : reg_t := (others => '0');
276 begin
277 -- Check that the register value equals the specified 'value'. Note that '-' can be used as a
278 -- wildcard in 'value' since check_match is used to check for equality.
279
280
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1176 read_reg(net, reg_index, got, base_address, bus_handle);
281
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1764 check_match(got, value, get_error_message(reg_index, base_address, message));
282 end procedure;
283
284
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18 procedure check_reg_equal(
285 signal net : inout network_t;
286 reg_index : in natural;
287 value : in integer;
288 base_address : in addr_t := (others => '0');
289 bus_handle : in bus_master_t := regs_bus_master;
290 message : in string := ""
291 ) is
292 2 variable got : integer := 0;
293 begin
294
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10 read_reg(net, reg_index, got, base_address, bus_handle);
295
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12 check_equal(got, value, get_error_message(reg_index, base_address, message), line_num => 295, file_name => "reg_operations_pkg.vhd");
296 end procedure;
297
298 procedure check_reg_equal_bits(
299 signal net : inout network_t;
300 reg_index : in natural;
301 bit_indexes : in natural_vec_t;
302 values : in std_logic_vector;
303 other_bits_value : in std_logic := '0';
304 base_address : in addr_t := (others => '0');
305 bus_handle : in bus_master_t := regs_bus_master;
306 message : in string := ""
307 ) is
308 variable reg_values : reg_t := (others => '0');
309 begin
310 -- Check that the bits in 'bit_indexes' have the expected 'values'.
311 -- Expected value of the other bits can be controlled with the 'other_bits_value' parameter.
312 -- Can set 'other_bits_value' to '-' to ignore all bits that are not designated
313 -- by 'bit_indexes'.
314
315 reg_values := to_reg_value(
316 bit_indexes=>bit_indexes,
317 values=>values,
318 previous_value=>(others => other_bits_value)
319 );
320
321 check_reg_equal(
322 net=>net,
323 reg_index=>reg_index,
324 value=>reg_values,
325 base_address=>base_address,
326 bus_handle=>bus_handle,
327 message=>message
328 );
329 end procedure;
330
331 procedure check_reg_equal_bit(
332 signal net : inout network_t;
333 reg_index : in natural;
334 bit_index : in natural;
335 value : in std_logic;
336 other_bits_value : in std_logic := '0';
337 base_address : in addr_t := (others => '0');
338 bus_handle : in bus_master_t := regs_bus_master;
339 message : in string := ""
340 ) is
341 begin
342 -- Check that the 'bit_index' bit has the expected 'value'.
343 -- Expected value of the other bits can be controlled with the 'other_bits_value' parameter.
344 -- Can set 'other_bits_value' to '-' to ignore all bits that are not designated by 'bit_index'.
345
346 check_reg_equal_bits(
347 net=>net,
348 reg_index=>reg_index,
349 bit_indexes=>(0 => bit_index),
350 values=>(0 => value),
351 other_bits_value=>other_bits_value,
352 base_address=>base_address,
353 bus_handle=>bus_handle,
354 message=>message
355 );
356 end procedure;
357
358
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112 procedure wait_until_reg_equals(
359 signal net : inout network_t;
360 reg_index : in natural;
361 value : in reg_t;
362 base_address : in addr_t := (others => '0');
363 bus_handle : in bus_master_t := regs_bus_master;
364 timeout : delay_length := max_timeout;
365 message : string := ""
366 ) is
367
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6 constant address : addr_t := base_address or to_unsigned(4 * reg_index, addr_t'length);
368 begin
369 -- Wait until the register has the specified 'value'. Note that '-' can be used as a wildcard
370 -- in 'value' since std_match is used to check for equality inside the VUnit function.
371
372
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112 wait_until_read_equals(
373 net=>net,
374 bus_handle=>bus_handle,
375 addr=>std_logic_vector(address),
376 value=>value,
377 timeout=>timeout,
378 msg=>get_error_message(reg_index, base_address, message)
379 );
380 end procedure;
381
382 procedure wait_until_reg_equals(
383 signal net : inout network_t;
384 reg_index : in natural;
385 value : in integer;
386 base_address : in addr_t := (others => '0');
387 bus_handle : in bus_master_t := regs_bus_master;
388 timeout : delay_length := max_timeout;
389 message : string := ""
390 ) is
391 begin
392 wait_until_reg_equals(
393 net=>net,
394 reg_index=>reg_index,
395 value=>std_logic_vector(to_signed(value, reg_width)),
396 base_address=>base_address,
397 bus_handle=>bus_handle,
398 timeout=>timeout,
399 message=>message
400 );
401 end procedure;
402
403
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112 procedure wait_until_reg_equals_bits(
404 signal net : inout network_t;
405 reg_index : in natural;
406 bit_indexes : in natural_vec_t;
407 values : in std_logic_vector;
408 other_bits_value : in std_logic := '-';
409 base_address : in addr_t := (others => '0');
410 bus_handle : in bus_master_t := regs_bus_master;
411 timeout : delay_length := max_timeout;
412 message : string := ""
413 ) is
414
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198 variable reg_value : reg_t := (others => '0');
415 begin
416 -- Wait until all the bits listed in 'bit_indexes' are read as their corresponding 'values'.
417 -- Other bits' values can either be ignored (if 'other_bits_value' is left at default value) or
418 -- checked against an expected value (by specifying 'other_bits_value').
419
420
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198 reg_value := to_reg_value(
421 bit_indexes=>bit_indexes,
422 values=>values,
423 previous_value=>(others => other_bits_value)
424 );
425
426
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112 wait_until_reg_equals(
427 net=>net,
428 reg_index=>reg_index,
429 value=>reg_value,
430 base_address=>base_address,
431 bus_handle=>bus_handle,
432 timeout=>timeout,
433 message=>message
434 );
435 end procedure;
436
437
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112 procedure wait_until_reg_equals_bit(
438 signal net : inout network_t;
439 reg_index : in natural;
440 bit_index : in natural;
441 value : in std_logic;
442 other_bits_value : in std_logic := '-';
443 base_address : in addr_t := (others => '0');
444 bus_handle : in bus_master_t := regs_bus_master;
445 timeout : delay_length := max_timeout;
446 message : string := ""
447 ) is
448 begin
449 -- Wait until the 'bit_index' bit is read as 'value'.
450 -- Other bits' values can either be ignored (if 'other_bits_value' is left at default value) or
451 -- checked against an expected value (by specifying 'other_bits_value').
452
453
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112 wait_until_reg_equals_bits(
454 net=>net,
455 reg_index=>reg_index,
456 bit_indexes=>(0 => bit_index),
457 values=>(0 => value),
458 other_bits_value=>other_bits_value,
459 base_address=>base_address,
460 bus_handle=>bus_handle,
461 timeout=>timeout,
462 message=>message
463 );
464 end procedure;
465
466
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816 procedure write_reg(
467 signal net : inout network_t;
468 reg_index : in natural;
469 value : in reg_t;
470 base_address : in addr_t := (others => '0');
471 bus_handle : in bus_master_t := regs_bus_master
472 ) is
473
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6666 variable address : addr_t;
474 begin
475 -- Note that this call is non-blocking.
476
477
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202 address := base_address or to_unsigned(4 * reg_index, address'length);
478
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816 write_bus(net, bus_handle, std_logic_vector(address), value);
479 end procedure;
480
481
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98 procedure write_reg(
482 signal net : inout network_t;
483 reg_index : in natural;
484 value : in integer;
485 base_address : in addr_t := (others => '0');
486 bus_handle : in bus_master_t := regs_bus_master
487 ) is
488 begin
489 -- Note that this call is non-blocking.
490
491
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98 write_reg(net, reg_index, std_logic_vector(to_signed(value, reg_width)), base_address, bus_handle);
492 end procedure;
493
494 procedure write_reg(
495 signal net : inout network_t;
496 reg_index : in natural;
497 value : in unsigned(reg_width - 1 downto 0);
498 base_address : in addr_t := (others => '0');
499 bus_handle : in bus_master_t := regs_bus_master
500 ) is
501 begin
502 -- Note that this call is non-blocking.
503
504 write_reg(net, reg_index, std_logic_vector(value), base_address, bus_handle);
505 end procedure;
506
507
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24 procedure write_reg_bits(
508 signal net : inout network_t;
509 reg_index : in natural;
510 bit_indexes : in natural_vec_t;
511 values : in std_logic_vector;
512 other_bits_value : in std_logic := '0';
513 base_address : in addr_t := (others => '0');
514 bus_handle : in bus_master_t := regs_bus_master
515 ) is
516
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198 variable reg_value : reg_t := (others => '0');
517 begin
518 -- Write to register where the bits listed in 'bit_indexes' will be set to 'values'.
519 -- The other bits in the write word are set to zero if 'other_bits_value' is left out,
520 -- or can be specified by assigning 'other_bits_value'.
521 -- Note that this call is non-blocking.
522
523
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198 reg_value := to_reg_value(
524 bit_indexes=>bit_indexes,
525 values=>values,
526 previous_value=>(others => other_bits_value)
527 );
528
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24 write_reg(
530 net=>net,
531 reg_index=>reg_index,
532 value=>reg_value,
533 base_address=>base_address,
534 bus_handle=>bus_handle
535 );
536 end procedure;
537
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24 procedure write_reg_bit(
539 signal net : inout network_t;
540 reg_index : in natural;
541 bit_index : in natural;
542 value : in std_logic;
543 other_bits_value : in std_logic := '0';
544 base_address : in addr_t := (others => '0');
545 bus_handle : in bus_master_t := regs_bus_master
546 ) is
547 begin
548 -- Write to register where the 'bit_index' bit will be set to 'value'.
549 -- The other bits in the write word are set to zero if 'other_bits_value' is left out,
550 -- or can be specified by assigning 'other_bits_value'.
551 -- Note that this call is non-blocking.
552
553
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24 write_reg_bits(
554 net=>net,
555 reg_index=>reg_index,
556 bit_indexes=>(0 => bit_index),
557 values=>(0 => value),
558 other_bits_value=>other_bits_value,
559 base_address=>base_address,
560 bus_handle=>bus_handle
561 );
562 end procedure;
563
564 procedure read_modify_write_reg_bits(
565 signal net : inout network_t;
566 reg_index : in natural;
567 bit_indexes : in natural_vec_t;
568 values : in std_logic_vector;
569 base_address : in addr_t := (others => '0');
570 bus_handle : in bus_master_t := regs_bus_master
571 ) is
572 variable previous_value, new_value : reg_t := (others => '0');
573 begin
574 -- Read-modify-write where the bits listed in 'bit_indexes' will be set to 'values'.
575 -- Note that the read portion of this call is blocking, but the write portion is non-blocking.
576
577 read_reg(
578 net=>net,
579 reg_index=>reg_index,
580 value=>previous_value,
581 base_address=>base_address,
582 bus_handle=>bus_handle
583 );
584
585 new_value := to_reg_value(bit_indexes, values, previous_value);
586
587 write_reg(
588 net=>net,
589 reg_index=>reg_index,
590 value=>new_value,
591 base_address=>base_address,
592 bus_handle=>bus_handle
593 );
594 end procedure;
595
596 procedure read_modify_write_reg_bit(
597 signal net : inout network_t;
598 reg_index : in natural;
599 bit_index : in natural;
600 value : in std_logic;
601 base_address : in addr_t := (others => '0');
602 bus_handle : in bus_master_t := regs_bus_master
603 ) is
604 begin
605 -- Read-modify-write where the 'bit_index' bit will be set to 'value'.
606 -- Note that the read portion of this call is blocking, but the write portion is non-blocking.
607
608 read_modify_write_reg_bits(
609 net=>net,
610 reg_index=>reg_index,
611 bit_indexes=>(0 => bit_index),
612 values=>(0 => value),
613 base_address=>base_address,
614 bus_handle=>bus_handle
615 );
616 end procedure;
617
618 function to_reg_value(
619 bit_indexes : natural_vec_t;
620 values : std_logic_vector;
621 previous_value : reg_t := (others => '0')
622 ) return reg_t is
623 20 variable result : reg_t := previous_value;
624 begin
625 -- Construct a register value based on bit values.
626 -- Assigning 'previous_value' realizes a "read-modify-write" behavior.
627
628 -- The natural_vec_t array is of integer range while std_logic_vector array is natural range.
629 -- This means that for literal inline arrays, bit_indexes will start at -2147483647 while
630 -- values will start at 0. Hence the handling is little more cumbersome.
631
632
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20 assert bit_indexes'left = bit_indexes'low report "Must use ascending array";
633
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20 assert values'left = values'low report "Must use ascending array";
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20 assert bit_indexes'length = values'length report "Arrays must be same length";
635
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20 for vec_index in 0 to bit_indexes'length - 1 loop
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30 result(bit_indexes(bit_indexes'low + vec_index)) := values(values'low + vec_index);
638 end loop;
639
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42 return result;
641 end function;
642
643 end;
644