tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/resync_cycles.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 72 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Resynchronizes a bit, so that the output bit is asserted as many
9 -- clock cycles as the input bit.
10 --
11 -- This module counts each clk_in cycle the input bit is asserted.
12 -- The counter is resynchronized to clk_out, and used as a reference to know
13 -- how many clk_out cycles the output bit should be asserted.
14 -- The module may fail when clk_out is slower than clk_in and the input is
15 -- asserted many cycles in a row. An assertion is made to check for this case.
16 --
17 -- Note that unlike e.g. resync_level, it is safe to drive the input of this entity with LUTs
18 -- as well as FFs.
19 -- -------------------------------------------------------------------------------------------------
20
21 library ieee;
22 use ieee.std_logic_1164.all;
23 use ieee.numeric_std.all;
24
25 library common;
26 use common.types_pkg.all;
27
28 library math;
29 use math.math_pkg.all;
30
31
32
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40222 entity resync_cycles is
33 generic (
34 counter_width : positive;
35 active_level : std_logic := '1'
36 );
37 port (
38 12 clk_in : in std_logic;
39
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78 data_in : in std_logic;
40
41 12 clk_out : in std_logic;
42
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144 data_out : out std_logic := (not active_level)
43 );
44 end entity;
45
46 architecture a of resync_cycles is
47 420 signal counter_in, counter_in_resync, counter_out : unsigned(counter_width - 1 downto 0) := (others => '0');
48 begin
49
50 ------------------------------------------------------------------------------
51 78 input : process
52 begin
53 40126 wait until rising_edge(clk_in);
54
55 10029 if data_in = active_level then
56 37338 counter_in <= (counter_in + 1);
57 end if;
58 end process;
59
60
61 ------------------------------------------------------------------------------
62
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124540 counter_in_resync_inst : entity work.resync_counter
63 generic map (
64 width => counter_width
65 )
66 port map (
67 clk_in => clk_in,
68 counter_in => counter_in,
69
70 clk_out => clk_out,
71 counter_out => counter_in_resync
72 );
73
74
75 ------------------------------------------------------------------------------
76 78 output : process
77 begin
78
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124384 wait until rising_edge(clk_out);
79
80
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31094 if counter_out /= counter_in_resync then
81
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8640 data_out <= active_level;
82
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34560 counter_out <= (counter_out + 1);
83 else
84
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124380 data_out <= not active_level;
85 end if;
86 end process;
87
88
89 ------------------------------------------------------------------------------
90 12 check_counter_wrapping : process
91 78 variable counter_in_p1 : unsigned(counter_in'range) := (others => '0');
92 begin
93
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62192 wait until rising_edge(clk_out);
94
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15547 if counter_in = counter_out then
96
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7987 assert counter_in_p1 = counter_in
97 report "Too many input cycles, outputs will be lost!";
98 end if;
99
100
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31106 counter_in_p1 := counter_in;
101 end process;
102
103 end architecture;
104