tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/resync_level_on_signal.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 8 8 100.0%
Branches: 14 18 77.8%

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1 204 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Sample a bit from one clock domain to another.
9 --
10 -- This modules does not utilize any meta stability protection.
11 -- It is up to the user to ensure that data_in is stable when sample_value is asserted.
12 --
13 -- Note that unlike e.g. resync_level, it is safe to drive the input of this entity with LUTs
14 -- as well as FFs.
15 -- -------------------------------------------------------------------------------------------------
16
17 library ieee;
18 use ieee.std_logic_1164.all;
19
20 library common;
21 use common.attribute_pkg.all;
22
23
24
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368 entity resync_level_on_signal is
25 generic (
26 -- Initial value for the ouput that will be set until the first input value has propagated
27 -- and been sampled.
28 default_value : std_logic := '0'
29 );
30 port (
31 data_in : in std_logic;
32
33 clk_out : in std_logic;
34 sample_value : in std_logic;
35 data_out : out std_logic := default_value
36 );
37 end entity;
38
39 architecture a of resync_level_on_signal is
40 68 signal data_in_int : std_logic;
41 attribute dont_touch of data_in_int : signal is "true"; -- Keep net so that we can apply constraint
42 begin
43
44
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6450 data_in_int <= data_in;
45
46
47 ------------------------------------------------------------------------------
48 34 main : process
49 begin
50
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6320 wait until rising_edge(clk_out);
51
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1577 if sample_value then
52
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3188 data_out <= data_in_int;
53 end if;
54 end process;
55
56 end architecture;
57