tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/resync_slv_level.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 5 5 100.0%
Branches: 5 7 71.4%

Line Branch Exec Source
1 96 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Resync a vector from one clock domain to another. This simple vector resync mechanism does not
9 -- guarantee any coherency between the bits. There might be a large skew between different bits.
10 --
11 -- See resync_level header for details about constraining.
12 -- -------------------------------------------------------------------------------------------------
13
14 library ieee;
15 use ieee.std_logic_1164.all;
16
17
18
4/5
✗ Branch 0 not taken.
✓ Branch 1 taken 104 times.
✓ Branch 2 taken 16 times.
✓ Branch 5 taken 88 times.
✓ Branch 6 taken 16 times.
480 entity resync_slv_level is
19 generic (
20 width : positive;
21 -- Enable or disable a register on the input side before the async_reg flip-flip chain.
22 -- Must be used if the input can contain glitches. See resync_slv header for more details.
23 -- The 'clk_in' port must be assigned if this generic is set to 'true'.
24 enable_input_register : boolean;
25 -- Initial value for the ouput that will be set for a few cycles before the first input
26 -- value has propagated.
27 default_value : std_logic_vector(width - 1 downto 0) := (others => '0')
28 );
29 port (
30 clk_in : in std_logic := '-';
31 data_in : in std_logic_vector(default_value'range);
32
33 clk_out : in std_logic;
34 data_out : out std_logic_vector(default_value'range) := default_value
35 );
36 end entity;
37
38 208 architecture a of resync_slv_level is
39 begin
40
41 ------------------------------------------------------------------------------
42 resync_gen : for i in data_in'range generate
43 120 begin
44
45 ------------------------------------------------------------------------------
46
1/2
✗ Branch 3 not taken.
✓ Branch 4 taken 88 times.
104 resync_level_inst : entity work.resync_level
47 generic map (
48 enable_input_register => enable_input_register,
49 default_value => default_value(i)
50 )
51 port map (
52 clk_in => clk_in,
53 data_in => data_in(i),
54
55 clk_out => clk_out,
56 data_out => data_out(i)
57 );
58
59 end generate;
60
61 end architecture;
62