tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/resync_slv_level_on_signal.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 9 9 100.0%
Branches: 6 8 75.0%

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1 42 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Sample a vector from one clock domain to another.
9 --
10 -- This modules does not utilize any meta stability protection.
11 -- It is up to the user to ensure that data_in is stable when sample_value is asserted.
12 --
13 -- Note that unlike e.g. resync_level, it is safe to drive the input of this entity with LUTs
14 -- as well as FFs.
15 -- -------------------------------------------------------------------------------------------------
16
17 library ieee;
18 use ieee.std_logic_1164.all;
19
20
21
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168 entity resync_slv_level_on_signal is
22 generic (
23 width : positive;
24 -- Initial value for the ouput that will be set until the first input
25 -- value has propagated and been sampled.
26 default_value : std_logic_vector(width - 1 downto 0) := (others => '0')
27 );
28 port (
29 data_in : in std_logic_vector(default_value'range);
30
31 28 clk_out : in std_logic;
32 sample_value : in std_logic;
33 28 data_out : out std_logic_vector(default_value'range) := default_value
34 28 );
35
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28 end entity;
36
37 70 architecture a of resync_slv_level_on_signal is
38 begin
39
40 ------------------------------------------------------------------------------
41 resync_gen : for i in data_in'range generate
42 42 begin
43
44 ------------------------------------------------------------------------------
45
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35 resync_on_signal_inst : entity work.resync_level_on_signal
46 generic map (
47 default_value => default_value(i)
48 )
49 port map (
50 data_in => data_in(i),
51
52 clk_out => clk_out,
53 sample_value => sample_value,
54 data_out => data_out(i)
55 );
56
57 end generate;
58
59 end architecture;
60