tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/artyz7/tb_artyz7_top.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 78 78 100.0%
Branches: 244 362 67.4%

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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.numeric_std.all;
11 use ieee.std_logic_1164.all;
12
13 library osvvm;
14 use osvvm.RandomPkg.all;
15
16 library vunit_lib;
17 use vunit_lib.memory_utils_pkg.all;
18 use vunit_lib.random_pkg.all;
19 context vunit_lib.vunit_context;
20 context vunit_lib.vc_context;
21
22 library common;
23 use common.addr_pkg.all;
24
25 library ddr_buffer;
26 use ddr_buffer.ddr_buffer_regs_pkg.all;
27 use ddr_buffer.ddr_buffer_sim_pkg.all;
28
29
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54 library reg_file;
30
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270 use reg_file.reg_file_pkg.all;
31 use reg_file.reg_operations_pkg.all;
32
33 use work.artyz7_top_pkg.all;
34 use work.artyz7_regs_pkg.all;
35 use work.top_level_sim_pkg.all;
36
37
38
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60 entity tb_artyz7_top is
39 generic (
40 runner_cfg : string
41 );
42 end entity;
43
44 architecture tb of tb_artyz7_top is
45
46 12 signal clk_ext : std_logic := '0';
47
48 begin
49
50 212 test_runner_watchdog(runner, 200 us);
51
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353 clk_ext <= not clk_ext after 8 ns;
52
53
54 ------------------------------------------------------------------------------
55 6 main : process
56
57 6 constant beef : reg_t := x"beef_beef";
58 6 constant dead : reg_t := x"dead_dead";
59 198 variable reg_value : reg_t := (others => '0');
60
61 6 constant axi_width : integer := 64;
62 6 constant burst_length : integer := 16;
63 6 constant burst_size_bytes : integer := burst_length * axi_width / 8;
64
65 6 variable rnd : RandomPType;
66 6 variable memory_data : integer_array_t := null_integer_array;
67 30 variable buf : buffer_t;
68 begin
69
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18 test_runner_setup(runner, runner_cfg);
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12 rnd.InitSeed(rnd'instance_name);
71
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6 if run("test_register_read_write") then
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3 write_reg(net, 0, beef, base_address => reg_slaves(0).addr);
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4 check_reg_equal(net, 0, beef, base_address => reg_slaves(0).addr);
75
76 -- Write different value to same register in another register map.
77 -- Should be in another clock domain to verify CDC.
78
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2 write_reg(net, 0, dead, base_address => reg_slaves(ddr_buffer_regs_idx).addr);
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4 check_reg_equal(net, 0, dead, base_address => reg_slaves(ddr_buffer_regs_idx).addr);
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5 check_reg_equal(net, 0, beef, base_address => reg_slaves(0).addr);
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5 elsif run("test_ddr_buffer") then
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7 run_ddr_buffer_test(net, axi_memory, rnd, ddr_buffer_regs_base_addr);
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3 check_expected_was_written(axi_memory);
86
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4 elsif run("test_generated_register_adresses") then
88 -- Default register
89
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2 check_equal(artyz7_config, 0, line_num => 89, file_name => "tb_artyz7_top.vhd");
90
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2 check_equal(artyz7_command, 1, line_num => 90, file_name => "tb_artyz7_top.vhd");
91
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2 check_equal(artyz7_status, 2, line_num => 91, file_name => "tb_artyz7_top.vhd");
92
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2 check_equal(artyz7_irq_status, 3, line_num => 92, file_name => "tb_artyz7_top.vhd");
93
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2 check_equal(artyz7_irq_mask, 4, line_num => 93, file_name => "tb_artyz7_top.vhd");
94
95 -- Plain register from TOML
96
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2 check_equal(artyz7_plain_dummy_reg, 5, line_num => 96, file_name => "tb_artyz7_top.vhd");
97
98 -- Register array from TOML
99
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2 check_equal(artyz7_dummy_regs_array_length, 3, line_num => 99, file_name => "tb_artyz7_top.vhd");
100
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2 check_equal(artyz7_dummy_regs_array_dummy_reg(0), 6, line_num => 101, file_name => "tb_artyz7_top.vhd");
102
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2 check_equal(artyz7_dummy_regs_second_array_dummy_reg(0), 7, line_num => 102, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_dummy_regs_array_dummy_reg(1), 8, line_num => 103, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_dummy_regs_second_array_dummy_reg(1), 9, line_num => 104, file_name => "tb_artyz7_top.vhd");
105
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2 check_equal(artyz7_dummy_regs_array_dummy_reg(2), 10, line_num => 105, file_name => "tb_artyz7_top.vhd");
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3 check_equal(artyz7_dummy_regs_second_array_dummy_reg(2), 11, line_num => 106, file_name => "tb_artyz7_top.vhd");
107
108
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3 elsif run("test_generated_register_modes") then
109 -- Default register
110
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1 assert artyz7_reg_map(artyz7_config).reg_type = r_w;
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1 assert artyz7_reg_map(artyz7_command).reg_type = wpulse;
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1 assert artyz7_reg_map(artyz7_status).reg_type = r;
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1 assert artyz7_reg_map(artyz7_irq_status).reg_type = r_wpulse;
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1 assert artyz7_reg_map(artyz7_irq_mask).reg_type = r_w;
115
116 -- Plain register from TOML
117
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1 assert artyz7_reg_map(artyz7_plain_dummy_reg).reg_type = r_w;
118
119 -- Register array from TOML
120
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1 assert artyz7_reg_map(artyz7_dummy_regs_array_dummy_reg(0)).reg_type = r_w;
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1 assert artyz7_reg_map(artyz7_dummy_regs_second_array_dummy_reg(0)).reg_type = r;
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1 assert artyz7_reg_map(artyz7_dummy_regs_array_dummy_reg(1)).reg_type = r_w;
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1 assert artyz7_reg_map(artyz7_dummy_regs_second_array_dummy_reg(1)).reg_type = r;
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1 assert artyz7_reg_map(artyz7_dummy_regs_array_dummy_reg(2)).reg_type = r_w;
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1 assert artyz7_reg_map(artyz7_dummy_regs_second_array_dummy_reg(2)).reg_type = r;
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2 elsif run("test_generated_register_field_indexes") then
128 -- Generated bit field indexes should match the order and widths in the TOML
129
130 -- Fields in the plain register
131
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2 check_equal(artyz7_plain_dummy_reg_plain_bit_a, 0, line_num => 131, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_plain_dummy_reg_plain_bit_b, 1, line_num => 132, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_plain_dummy_reg_plain_bit_vector'low, 2, line_num => 133, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_plain_dummy_reg_plain_bit_vector'high, 5, line_num => 134, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_plain_dummy_reg_plain_bit_vector_width, 4, line_num => 135, file_name => "tb_artyz7_top.vhd");
136
137 -- Fields in the register array register
138
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2 check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_a, 0, line_num => 138, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_b, 1, line_num => 139, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_vector'low, 2, line_num => 140, file_name => "tb_artyz7_top.vhd");
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2 check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_vector'high, 6, line_num => 141, file_name => "tb_artyz7_top.vhd");
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3 check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_vector_width, 5, line_num => 142, file_name => "tb_artyz7_top.vhd");
143
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7 elsif run("test_generated_register_default_values") then
145 -- Test reading the default values set in the regs TOML
146
147
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5 read_reg(
148 net,
149 artyz7_plain_dummy_reg,
150 reg_value,
151 base_address => reg_slaves(0).addr
152 );
153
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2 check_equal(reg_value(artyz7_plain_dummy_reg_plain_bit_a), '0', line_num => 154, file_name => "tb_artyz7_top.vhd");
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2 check_equal(reg_value(artyz7_plain_dummy_reg_plain_bit_b), '1', line_num => 155, file_name => "tb_artyz7_top.vhd");
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2 check_equal(unsigned(reg_value(artyz7_plain_dummy_reg_plain_bit_vector)), 3, line_num => 156, file_name => "tb_artyz7_top.vhd");
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1 for register_array_idx in 0 to 3 - 1 loop
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12 read_reg(
160 net,
161 artyz7_dummy_regs_array_dummy_reg(register_array_idx),
162 reg_value,
163 base_address => reg_slaves(0).addr
164 );
165
166
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6 check_equal(reg_value(artyz7_dummy_regs_array_dummy_reg_array_bit_a), '1', line_num => 166, file_name => "tb_artyz7_top.vhd");
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6 check_equal(reg_value(artyz7_dummy_regs_array_dummy_reg_array_bit_b), '0', line_num => 167, file_name => "tb_artyz7_top.vhd");
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13 check_equal(unsigned(reg_value(artyz7_dummy_regs_array_dummy_reg_array_bit_vector)), 12, line_num => 168, file_name => "tb_artyz7_top.vhd");
169 end loop;
170
171 end if;
172
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150 test_runner_cleanup(runner);
174 end process;
175
176
177 ------------------------------------------------------------------------------
178 12 dut : entity work.artyz7_top
179 port map (
180 clk_ext => clk_ext
181 );
182
183 end architecture;
184