tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_cdc.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Test AXI clock domain crossing by running transactions through a
9 -- axi_read/write_cdc -> axi_read/write_throttle chain. The tests run are not very exhaustive,
10 -- it is more of a connectivity test.
11 -- -------------------------------------------------------------------------------------------------
12
13 library ieee;
14 use ieee.std_logic_1164.all;
15 use ieee.numeric_std.all;
16
17 library vunit_lib;
18 use vunit_lib.memory_pkg.all;
19 context vunit_lib.vunit_context;
20 context vunit_lib.vc_context;
21
22 library osvvm;
23 use osvvm.RandomPkg.all;
24
25 library bfm;
26
27 use work.axi_pkg.all;
28
29
30
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197048 entity tb_axi_cdc is
31 generic (
32
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1542 input_clk_fast : boolean := false;
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3474 output_clk_fast : boolean := false;
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3552 max_burst_length_beats : positive;
35
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774 runner_cfg : string
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1854 );
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1620 end entity;
38 318
39
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1224 architecture tb of tb_axi_cdc is
40 930
41
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3246 constant id_width : natural := 5;
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168 constant addr_width : positive := 24;
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12 constant data_width : positive := 32;
44 6 constant num_words : positive := 1000;
45
46 6 constant clk_fast_period : time := 3 ns;
47 6 constant clk_slow_period : time := 7 ns;
48 12
49 6 signal clk_input, clk_output : std_logic := '0';
50 12
51 612 signal input_read_m2s : axi_read_m2s_t := axi_read_m2s_init;
52
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3162 signal input_read_s2m : axi_read_s2m_t := axi_read_s2m_init;
53 2172
54 1620 signal input_write_m2s : axi_write_m2s_t := axi_write_m2s_init;
55
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4614 signal input_write_s2m : axi_write_s2m_t := axi_write_s2m_init;
56 1092
57 6 constant axi_master : bus_master_t := new_bus(
58 data_length => data_width,
59 address_length => input_read_m2s.ar.addr'length
60 );
61
62 6 constant memory : memory_t := new_memory;
63 6 constant axi_slave : axi_slave_t := new_axi_slave(
64 memory => memory,
65 address_fifo_depth => 4,
66 write_response_fifo_depth => 4,
67 address_stall_probability => 0.3,
68 data_stall_probability => 0.3,
69 write_response_stall_probability => 0.3,
70 min_response_latency => 8 * clk_fast_period,
71 max_response_latency => 16 * clk_slow_period,
72 logger => get_logger("axi_slave")
73 );
74
75 begin
76
77 clk_input_gen : if input_clk_fast generate
78 379254 clk_input <= not clk_input after clk_fast_period / 2;
79 else generate
80 182258 clk_input <= not clk_input after clk_slow_period / 2;
81 end generate;
82
83 clk_output_gen : if output_clk_fast generate
84 186032 clk_output <= not clk_output after clk_fast_period / 2;
85 else generate
86
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186970 clk_output <= not clk_output after clk_slow_period / 2;
87 end generate;
88
89
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42132 test_runner_watchdog(runner, 1 ms);
90
91
92 ------------------------------------------------------------------------------
93 6 main : process
94 6 variable rnd : RandomPType;
95 198 variable data : std_logic_vector(data_width - 1 downto 0);
96 6 variable address : integer;
97 30 variable buf : buffer_t;
98 begin
99
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18 test_runner_setup(runner, runner_cfg);
100
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12 rnd.InitSeed(rnd'instance_name);
101
102 6 buf := allocate(memory, 4 * num_words);
103
104
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6 if run("test_read") then
105 3 for idx in 0 to num_words - 1 loop
106 3000 address := 4 * idx;
107
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3000 data := rnd.RandSlv(data'length);
108
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6000 write_word(memory, address, data);
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18006 check_bus(net, axi_master, address, data);
111 end loop;
112
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9 elsif run("test_write") then
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3 for idx in 0 to num_words - 1 loop
115 3000 address := 4 * idx;
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3000 data := rnd.RandSlv(data'length);
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6000 set_expected_word(memory, address, data);
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12003 write_bus(net, axi_master, address, data);
120 end loop;
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12 wait_until_idle(net, as_sync(axi_master));
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9 check_expected_was_written(memory);
124 end if;
125
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36072 test_runner_cleanup(runner);
127 end process;
128
129
130 ------------------------------------------------------------------------------
131 6 axi_master_inst : entity bfm.axi_master
132 generic map (
133 bus_handle => axi_master
134 )
135 port map (
136 clk => clk_input,
137 --
138 axi_read_m2s => input_read_m2s,
139 axi_read_s2m => input_read_s2m,
140 --
141 axi_write_m2s => input_write_m2s,
142 axi_write_s2m => input_write_s2m
143 );
144
145
146 ------------------------------------------------------------------------------
147 read_block : block
148 1218 signal resynced_m2s, throttled_m2s : axi_read_m2s_t := axi_read_m2s_init;
149 1854 signal resynced_s2m, throttled_s2m : axi_read_s2m_t := axi_read_s2m_init;
150
151 6 constant data_fifo_depth : positive := 1024;
152 6 signal data_fifo_level : integer range 0 to data_fifo_depth := 0;
153 begin
154
155 ------------------------------------------------------------------------------
156 6 axi_read_cdc_inst : entity work.axi_read_cdc
157 generic map (
158 id_width => id_width,
159 addr_width => addr_width,
160 data_width => data_width,
161 enable_data_fifo_packet_mode => false,
162 data_fifo_depth => data_fifo_depth,
163 address_fifo_depth => 32
164 )
165 port map (
166 clk_input => clk_input,
167 input_m2s => input_read_m2s,
168 input_s2m => input_read_s2m,
169 --
170 clk_output => clk_output,
171 output_m2s => resynced_m2s,
172 output_s2m => resynced_s2m,
173 output_data_fifo_level => data_fifo_level
174 );
175
176
177 ------------------------------------------------------------------------------
178
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6 axi_read_throttle_inst : entity work.axi_read_throttle
179 generic map (
180 data_fifo_depth => data_fifo_depth,
181 max_burst_length_beats => max_burst_length_beats,
182 id_width => id_width,
183 addr_width => addr_width,
184 full_ar_throughput => false
185 )
186 port map (
187 clk => clk_output,
188 --
189 data_fifo_level => data_fifo_level,
190 --
191 input_m2s => resynced_m2s,
192 input_s2m => resynced_s2m,
193 --
194 throttled_m2s => throttled_m2s,
195 throttled_s2m => throttled_s2m
196 );
197
198
199 ------------------------------------------------------------------------------
200 6 axi_read_slave_wrapper_inst : entity bfm.axi_read_slave
201 generic map (
202 axi_slave => axi_slave,
203 data_width => data_width,
204 id_width => id_width
205 )
206 port map (
207 clk => clk_output,
208 --
209 axi_read_m2s => throttled_m2s,
210 axi_read_s2m => throttled_s2m
211 );
212
213 end block;
214
215
216 ------------------------------------------------------------------------------
217 write_block : block
218 3234 signal resynced_m2s, throttled_m2s : axi_write_m2s_t := axi_write_m2s_init;
219 318 signal resynced_s2m, throttled_s2m : axi_write_s2m_t := axi_write_s2m_init;
220
221 6 constant data_fifo_depth : positive := 1024;
222 12 signal data_fifo_level : integer range 0 to data_fifo_depth := 0;
223 begin
224
225 ------------------------------------------------------------------------------
226 6 axi_write_cdc_inst : entity work.axi_write_cdc
227 generic map (
228 id_width => id_width,
229 addr_width => addr_width,
230 data_width => data_width,
231 enable_data_fifo_packet_mode => true,
232 address_fifo_depth => 32,
233 data_fifo_depth => data_fifo_depth,
234 response_fifo_depth => 32
235 )
236 port map (
237 clk_input => clk_input,
238 input_m2s => input_write_m2s,
239 input_s2m => input_write_s2m,
240 --
241 clk_output => clk_output,
242 output_m2s => resynced_m2s,
243 output_s2m => resynced_s2m,
244 output_data_fifo_level => data_fifo_level
245 );
246
247
248 ------------------------------------------------------------------------------
249
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6 axi_write_throttle_inst : entity work.axi_write_throttle
250 generic map (
251 data_fifo_depth => data_fifo_depth,
252 max_burst_length_beats => max_burst_length_beats,
253 id_width => id_width,
254 addr_width => addr_width,
255 full_aw_throughput => false
256 )
257 port map (
258 clk => clk_output,
259 --
260 data_fifo_level => data_fifo_level,
261 --
262 input_m2s => resynced_m2s,
263 input_s2m => resynced_s2m,
264 --
265 throttled_m2s => throttled_m2s,
266 throttled_s2m => throttled_s2m
267 );
268
269
270 ------------------------------------------------------------------------------
271 12 axi_write_slave_wrapper_inst : entity bfm.axi_write_slave
272 generic map (
273 axi_slave => axi_slave,
274 data_width => data_width,
275 id_width => id_width
276 )
277 port map (
278 clk => clk_output,
279 --
280 axi_write_m2s => throttled_m2s,
281 axi_write_s2m => throttled_s2m
282 );
283
284 end block;
285
286 end architecture;
287