tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_fifo.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 use vunit_lib.memory_pkg.all;
15 context vunit_lib.vunit_context;
16 context vunit_lib.vc_context;
17
18 library osvvm;
19 use osvvm.RandomPkg.all;
20
21 library bfm;
22
23 use work.axi_pkg.all;
24
25
26
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60 entity tb_axi_fifo is
27 generic (
28 depth : natural;
29 6 asynchronous : boolean := false;
30 runner_cfg : string
31
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1218 );
32
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930 end entity;
33 12
34
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5790 architecture tb of tb_axi_fifo is
35 180
36
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1866 constant data_width : integer := 32;
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4626 constant id_width : integer := 5;
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624 constant num_words : integer := 1000;
39 2790
40
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24 constant clk_fast_period : time := 3 ns;
41
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1632 constant clk_slow_period : time := 7 ns;
42 318
43 12 signal clk_input, clk_output : std_logic := '0';
44 6
45 1218 signal input_read_m2s, output_read_m2s : axi_read_m2s_t := axi_read_m2s_init;
46 1854 signal input_read_s2m, output_read_s2m : axi_read_s2m_t := axi_read_s2m_init;
47 3234 signal input_write_m2s, output_write_m2s : axi_write_m2s_t := axi_write_m2s_init;
48 318 signal input_write_s2m, output_write_s2m : axi_write_s2m_t := axi_write_s2m_init;
49
50 6 constant axi_master : bus_master_t := new_bus(
51 data_length => data_width,
52 address_length => input_read_m2s.ar.addr'length
53 );
54
55 6 constant memory : memory_t := new_memory;
56 6 constant axi_read_slave, axi_write_slave : axi_slave_t := new_axi_slave(
57 memory => memory,
58 address_fifo_depth => 4,
59 write_response_fifo_depth => 4,
60 address_stall_probability => 0.3,
61 data_stall_probability => 0.3,
62 write_response_stall_probability => 0.3,
63 min_response_latency => 8 * clk_fast_period,
64 max_response_latency => 16 * clk_slow_period,
65 logger => get_logger("axi_slave")
66 );
67
68 begin
69
70 186968 test_runner_watchdog(runner, 1 ms);
71
72 clk_input_gen : if asynchronous generate
73 186934 clk_input <= not clk_input after clk_fast_period / 2;
74 80114 clk_output <= not clk_output after clk_slow_period / 2;
75 else generate
76 236448 clk_input <= not clk_input after clk_fast_period / 2;
77
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278526 clk_output <= not clk_output after clk_fast_period / 2;
78 end generate;
79
80 ------------------------------------------------------------------------------
81 6 main : process
82 6 variable rnd : RandomPType;
83 198 variable data : std_logic_vector(data_width - 1 downto 0);
84 6 variable address : integer;
85 30 variable buf : buffer_t;
86 begin
87
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18 test_runner_setup(runner, runner_cfg);
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12 rnd.InitSeed(rnd'instance_name);
89
90 6 buf := allocate(memory, 4 * num_words);
91
92
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6 if run("test_read") then
93 3 for idx in 0 to num_words - 1 loop
94 3000 address := 4 * idx;
95
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3000 data := rnd.RandSlv(data'length);
96
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6000 write_word(memory, address, data);
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18006 check_bus(net, axi_master, address, data);
99 end loop;
100
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9 elsif run("test_write") then
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103 3000 address := 4 * idx;
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3000 data := rnd.RandSlv(data'length);
105
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6000 set_expected_word(memory, address, data);
106
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12003 write_bus(net, axi_master, address, data);
108 end loop;
109
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12 wait_until_idle(net, as_sync(axi_master));
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9 check_expected_was_written(memory);
112 end if;
113
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36072 test_runner_cleanup(runner);
115 end process;
116
117
118 ------------------------------------------------------------------------------
119 6 axi_input_inst : entity bfm.axi_master
120 generic map (
121 bus_handle => axi_master
122 )
123 port map (
124 clk => clk_input,
125 --
126 axi_read_m2s => input_read_m2s,
127 axi_read_s2m => input_read_s2m,
128 --
129 axi_write_m2s => input_write_m2s,
130 axi_write_s2m => input_write_s2m
131 );
132
133
134 ------------------------------------------------------------------------------
135 6 axi_output_inst : entity bfm.axi_slave
136 generic map (
137 axi_read_slave => axi_read_slave,
138 axi_write_slave => axi_write_slave,
139 data_width => data_width,
140 id_width => id_width
141 )
142 port map (
143 clk => clk_output,
144 --
145 axi_read_m2s => output_read_m2s,
146 axi_read_s2m => output_read_s2m,
147 --
148 axi_write_m2s => output_write_m2s,
149 axi_write_s2m => output_write_s2m
150 );
151
152
153 ------------------------------------------------------------------------------
154 6 axi_ar_fifo_inst : entity work.axi_address_fifo
155 generic map (
156 id_width => id_width,
157 addr_width => 32,
158 asynchronous => asynchronous,
159 depth => depth
160 )
161 port map (
162 clk => clk_output,
163 --
164 input_m2s => input_read_m2s.ar,
165 input_s2m => input_read_s2m.ar,
166 --
167 output_m2s => output_read_m2s.ar,
168 output_s2m => output_read_s2m.ar,
169 --
170 clk_input => clk_input
171 );
172
173
174 ------------------------------------------------------------------------------
175 6 axi_r_fifo_inst : entity work.axi_r_fifo
176 generic map (
177 id_width => id_width,
178 data_width => data_width,
179 asynchronous => asynchronous,
180 depth => depth
181 )
182 port map (
183 clk => clk_output,
184 --
185 input_m2s => input_read_m2s.r,
186 input_s2m => input_read_s2m.r,
187 --
188 output_m2s => output_read_m2s.r,
189 output_s2m => output_read_s2m.r,
190 --
191 clk_input => clk_input
192 );
193
194
195 ------------------------------------------------------------------------------
196 6 axi_aw_fifo_inst : entity work.axi_address_fifo
197 generic map (
198 id_width => id_width,
199 addr_width => 32,
200 asynchronous => asynchronous,
201 depth => depth
202 )
203 port map (
204 clk => clk_output,
205 --
206 input_m2s => input_write_m2s.aw,
207 input_s2m => input_write_s2m.aw,
208 --
209 output_m2s => output_write_m2s.aw,
210 output_s2m => output_write_s2m.aw,
211 --
212 clk_input => clk_input
213 );
214
215
216 ------------------------------------------------------------------------------
217 6 axi_w_fifo_inst : entity work.axi_w_fifo
218 generic map (
219 data_width => data_width,
220 asynchronous => asynchronous,
221 depth => depth
222 )
223 port map (
224 clk => clk_output,
225 --
226 input_m2s => input_write_m2s.w,
227 input_s2m => input_write_s2m.w,
228 --
229 output_m2s => output_write_m2s.w,
230 output_s2m => output_write_s2m.w,
231 --
232 clk_input => clk_input
233 );
234
235
236 ------------------------------------------------------------------------------
237 12 axi_b_fifo_inst : entity work.axi_b_fifo
238 generic map (
239 id_width => id_width,
240 asynchronous => asynchronous,
241 depth => depth
242 )
243 port map (
244 clk => clk_output,
245 --
246 input_m2s => input_write_m2s.b,
247 input_s2m => input_write_s2m.b,
248 --
249 output_m2s => output_write_m2s.b,
250 output_s2m => output_write_s2m.b,
251 --
252 clk_input => clk_input
253 );
254
255 end architecture;
256