tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_lite_cdc.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 18 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 use vunit_lib.memory_pkg.all;
15 context vunit_lib.vunit_context;
16 context vunit_lib.vc_context;
17
18 library osvvm;
19 use osvvm.RandomPkg.all;
20
21 library bfm;
22
23 use work.axi_pkg.all;
24 use work.axi_lite_pkg.all;
25
26
27
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30 entity tb_axi_lite_cdc is
28 generic (
29 3 master_clk_fast : boolean := false;
30 slave_clk_fast : boolean := false;
31
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1203 runner_cfg : string
32
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207 );
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603 end entity;
34 411
35
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195 architecture tb of tb_axi_lite_cdc is
36 399
37
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1206 constant data_width : integer := 32;
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621 constant addr_width : integer := 24;
39
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18 constant num_words : integer := 2048;
40
41 3 constant clk_fast_period : time := 3 ns;
42 3 constant clk_slow_period : time := 7 ns;
43
44 3 signal clk_master, clk_slave : std_logic := '0';
45
46 1203 signal master_m2s, slave_m2s : axi_lite_m2s_t := axi_lite_m2s_init;
47 411 signal master_s2m, slave_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
48
49 3 constant axi_lite_master : bus_master_t := new_bus(
50 data_length => data_width,
51 address_length => master_m2s.read.ar.addr'length
52 );
53
54 3 constant memory : memory_t := new_memory;
55 3 constant axi_lite_read_slave, axi_lite_write_slave : axi_slave_t := new_axi_slave(
56 memory => memory,
57 address_fifo_depth => 8,
58 write_response_fifo_depth => 8,
59 address_stall_probability => 0.3,
60 data_stall_probability => 0.3,
61 write_response_stall_probability => 0.3,
62 min_response_latency => 8 * clk_fast_period,
63 max_response_latency => 16 * clk_slow_period,
64 logger => get_logger("axi_lite_slave_slave")
65 );
66
67 begin
68
69 380509 test_runner_watchdog(runner, 1 ms);
70
71 clk_master_gen : if master_clk_fast generate
72 380492 clk_master <= not clk_master after clk_fast_period / 2;
73 else generate
74 361624 clk_master <= not clk_master after clk_slow_period / 2;
75 end generate;
76
77 clk_slave_gen : if slave_clk_fast generate
78 371940 clk_slave <= not clk_slave after clk_fast_period / 2;
79 else generate
80
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463624 clk_slave <= not clk_slave after clk_slow_period / 2;
81 end generate;
82
83
84 ------------------------------------------------------------------------------
85 3 main : process
86 3 variable rnd : RandomPType;
87 99 variable data : std_logic_vector(data_width - 1 downto 0);
88 3 variable address : integer;
89 15 variable buf : buffer_t;
90 begin
91
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9 test_runner_setup(runner, runner_cfg);
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6 rnd.InitSeed(rnd'instance_name);
93
94 3 buf := allocate(memory, 4 * num_words);
95
96
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3 for idx in 0 to num_words - 1 loop
97 6144 address := 4 * idx;
98
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6144 data := rnd.RandSlv(data'length);
99
100 -- Call is non-blocking. I.e. we will build up a queue of writes.
101
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18432 write_bus(net, axi_lite_master, address, data);
102
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12288 set_expected_word(memory, address, data);
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30717 wait until rising_edge(clk_master);
104 end loop;
105
106
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3 for idx in 0 to num_words - 1 loop
107 6144 address := 4 * idx;
108
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6144 data := read_word(memory, address, 4);
109
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36867 check_bus(net, axi_lite_master, address, data);
111 end loop;
112
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67611 test_runner_cleanup(runner);
114 end process;
115
116
117 ------------------------------------------------------------------------------
118 3 axi_lite_master_inst : entity bfm.axi_lite_master
119 generic map (
120 bus_handle => axi_lite_master
121 )
122 port map (
123 clk => clk_master,
124
125 axi_lite_m2s => master_m2s,
126 axi_lite_s2m => master_s2m
127 );
128
129
130 ------------------------------------------------------------------------------
131 3 axi_lite_slave_inst : entity bfm.axi_lite_slave
132 generic map (
133 axi_read_slave => axi_lite_read_slave,
134 axi_write_slave => axi_lite_write_slave,
135 data_width => data_width
136 )
137 port map (
138 clk => clk_slave,
139 --
140 axi_lite_read_m2s => slave_m2s.read,
141 axi_lite_read_s2m => slave_s2m.read,
142 --
143 axi_lite_write_m2s => slave_m2s.write,
144 axi_lite_write_s2m => slave_s2m.write
145 );
146
147
148
149 ------------------------------------------------------------------------------
150 6 dut : entity work.axi_lite_cdc
151 generic map (
152 data_width => data_width,
153 addr_width => addr_width
154 )
155 port map (
156 clk_master => clk_master,
157 master_m2s => master_m2s,
158 master_s2m => master_s2m,
159
160 clk_slave => clk_slave,
161 slave_m2s => slave_m2s,
162 slave_s2m => slave_s2m
163 );
164
165 end architecture;
166