tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_lite_mux.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 108 108 100.0%
Branches: 431 593 72.7%

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1 18 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 use vunit_lib.memory_pkg.all;
15 context vunit_lib.vunit_context;
16 context vunit_lib.vc_context;
17
18 library osvvm;
19 use osvvm.RandomPkg.all;
20
21 library bfm;
22 use bfm.bfm_pkg.all;
23
24 library common;
25 use common.addr_pkg.all;
26
27 use work.axi_lite_pkg.all;
28
29
30
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30 entity tb_axi_lite_mux is
31 generic (
32
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69 use_axi_lite_bfm : boolean := true;
33 12 runner_cfg : string
34 );
35
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780 end entity;
36 1596
37 architecture tb of tb_axi_lite_mux is
38 1644
39
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63 constant data_width : integer := 32;
40 3 constant bytes_per_word : integer := data_width / 8;
41
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606 constant num_slaves : integer := 4;
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411 subtype slaves_rng is integer range 0 to num_slaves - 1;
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44
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4842 constant num_words : integer := 32;
45
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834 constant addr_offset : integer := 4096; -- Corresponding to the base addresses below
46
47 3 constant slave_addrs : addr_and_mask_vec_t(slaves_rng) := (
48 (addr => x"0000_0000", mask => x"0000_7000"),
49 (addr => x"0000_1000", mask => x"0000_7000"),
50 (addr => x"0000_2000", mask => x"0000_7000"),
51 (addr => x"0000_3000", mask => x"0000_7000")
52 );
53
54 3 constant clk_period : time := 10 ns;
55 3 signal clk : std_logic := '0';
56
57 1203 signal axi_lite_m2s, hard_coded_m2s : axi_lite_m2s_t;
58 207 signal axi_lite_s2m : axi_lite_s2m_t;
59
60 2415 signal axi_lite_m2s_vec : axi_lite_m2s_vec_t(slaves_rng);
61 831 signal axi_lite_s2m_vec : axi_lite_s2m_vec_t(slaves_rng);
62
63 3 constant axi_master : bus_master_t := new_bus(data_length => data_width, address_length => axi_lite_m2s.read.ar.addr'length);
64
65 3 constant memory : memory_vec_t(slaves_rng) := get_new_memories(num_slaves);
66
67 27 constant axi_read_slave, axi_write_slave : axi_slave_vec_t(slaves_rng) := (
68 0 => new_axi_slave(address_fifo_depth => 1, memory => memory(0)),
69 1 => new_axi_slave(address_fifo_depth => 1, memory => memory(1)),
70 2 => new_axi_slave(address_fifo_depth => 1, memory => memory(2)),
71 3 => new_axi_slave(address_fifo_depth => 1, memory => memory(3))
72 );
73
74 begin
75
76 2381 test_runner_watchdog(runner, 2 ms);
77 2363 clk <= not clk after clk_period / 2;
78
79
80 ------------------------------------------------------------------------------
81 3 main : process
82
83 function bank_address(slave, word : integer) return integer is
84 begin
85 272 return slave * addr_offset + word * bytes_per_word;
86 end function;
87
88
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51 procedure hard_coded_read_data(addr : in unsigned(slave_addrs(0).addr'range)) is
89 begin
90
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4 hard_coded_m2s.read.ar.valid <= '1';
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260 hard_coded_m2s.read.ar.addr <= x"0000_0000" & addr;
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31 wait until (axi_lite_s2m.read.ar.ready and axi_lite_m2s.read.ar.valid) = '1' and rising_edge(clk);
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4 hard_coded_m2s.read.ar.valid <= '0';
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4 hard_coded_m2s.read.r.ready <= '1';
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20 wait until (axi_lite_m2s.read.r.ready and axi_lite_s2m.read.r.valid) = '1' and rising_edge(clk);
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16 hard_coded_m2s.read.r.ready <= '0';
98 end procedure;
99
100
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67 procedure hard_coded_write_data(addr : in unsigned(slave_addrs(0).addr'range);
101 data : in std_logic_vector(data_width - 1 downto 0)) is
102 begin
103
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4 hard_coded_m2s.write.aw.valid <= '1';
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260 hard_coded_m2s.write.aw.addr <= x"0000_0000" & addr;
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31 wait until (axi_lite_s2m.write.aw.ready and axi_lite_m2s.write.aw.valid) = '1' and rising_edge(clk);
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4 hard_coded_m2s.write.aw.valid <= '0';
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4 hard_coded_m2s.write.w.valid <= '1';
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260 hard_coded_m2s.write.w.data <= x"0000_0000" & data;
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36 hard_coded_m2s.write.w.strb <= x"0f";
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20 wait until (axi_lite_s2m.write.w.ready and axi_lite_m2s.write.w.valid) = '1' and rising_edge(clk);
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4 hard_coded_m2s.write.w.valid <= '0';
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20 wait until (axi_lite_m2s.write.b.ready and axi_lite_s2m.write.b.valid) = '1' and rising_edge(clk);
116
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2275 hard_coded_m2s.write.b.ready <= '0';
117 end procedure;
118
119 3 variable rnd : RandomPType;
120 99 variable data : std_logic_vector(data_width - 1 downto 0);
121 3 variable address : integer;
122 615 variable buf : buffer_t;
123
124 begin
125
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9 test_runner_setup(runner, runner_cfg);
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6 rnd.InitSeed(rnd'instance_name);
127
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3 for slave_idx in memory'range loop
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12 buf := allocate(memory(slave_idx), bank_address(slave_idx, num_words));
130 end loop;
131
132
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3 if run("read_and_write_to_buffer") then
133 1 for slave_idx in memory'range loop
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4 for word in 0 to num_words - 1 loop
135 128 address := bank_address(slave_idx, word);
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128 data := rnd.RandSLV(data'length);
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256 set_expected_word(memory(slave_idx), address, data);
138
139 -- Call is non-blocking. I.e. we will build up a queue of writes.
140
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384 write_bus(net, axi_master, address, data);
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647 wait until rising_edge(clk);
142 end loop;
143 end loop;
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5 wait_until_idle(net, as_sync(axi_master));
145
146 -- Test that everything was written correctly to memory
147
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16 check_expected_was_written(memory(slave_idx));
149 end loop;
150
151 -- Test reading back data
152
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4 for word in 0 to num_words - 1 loop
154 128 address := bank_address(slave_idx, word);
155
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128 data := read_word(memory(slave_idx), address, 4);
156
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777 check_bus(net, axi_master, address, data);
158 end loop;
159 end loop;
160
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2 elsif run("read_from_non_existent_slave_base_address") then
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10 hard_coded_read_data(x"0000_4000");
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2 check_equal(axi_lite_s2m.read.r.resp, axi_resp_decerr, line_num => 163, file_name => "tb_axi_lite_mux.vhd");
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1 data := rnd.RandSLV(data'length);
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2 write_word(memory(0), bank_address(0, 0), data);
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11 hard_coded_read_data(slave_addrs(0).addr);
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2 check_equal(axi_lite_s2m.read.r.resp, axi_resp_okay, line_num => 168, file_name => "tb_axi_lite_mux.vhd");
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2 check_equal(axi_lite_s2m.read.r.data(data'range), data, line_num => 169, file_name => "tb_axi_lite_mux.vhd");
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11 hard_coded_read_data(x"0000_5000");
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2 check_equal(axi_lite_s2m.read.r.resp, axi_resp_decerr, line_num => 172, file_name => "tb_axi_lite_mux.vhd");
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1 data := rnd.RandSLV(data'length);
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2 write_word(memory(1), bank_address(1, 0), data);
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11 hard_coded_read_data(slave_addrs(1).addr);
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2 check_equal(axi_lite_s2m.read.r.resp, axi_resp_okay, line_num => 177, file_name => "tb_axi_lite_mux.vhd");
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3 check_equal(axi_lite_s2m.read.r.data(data'range), data, line_num => 178, file_name => "tb_axi_lite_mux.vhd");
179
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4 elsif run("write_to_non_existent_slave_base_address") then
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13 hard_coded_write_data(x"0000_4000", x"0102_0304");
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2 check_equal(axi_lite_s2m.write.b.resp, axi_resp_decerr, line_num => 182, file_name => "tb_axi_lite_mux.vhd");
183
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1 data := rnd.RandSLV(data'length);
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2 set_expected_word(memory(0), bank_address(0, 0), data);
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14 hard_coded_write_data(slave_addrs(0).addr, data);
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2 check_equal(axi_lite_s2m.write.b.resp, axi_resp_okay, line_num => 187, file_name => "tb_axi_lite_mux.vhd");
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2 check_expected_was_written(memory(0));
189
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14 hard_coded_write_data(x"0000_5000", x"0102_0304");
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2 check_equal(axi_lite_s2m.write.b.resp, axi_resp_decerr, line_num => 191, file_name => "tb_axi_lite_mux.vhd");
192
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1 data := rnd.RandSLV(data'length);
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2 set_expected_word(memory(1), bank_address(1, 0), data);
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14 hard_coded_write_data(slave_addrs(1).addr, data);
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2 check_equal(axi_lite_s2m.write.b.resp, axi_resp_okay, line_num => 196, file_name => "tb_axi_lite_mux.vhd");
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3 check_expected_was_written(memory(1));
198 end if;
199
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1528 test_runner_cleanup(runner);
201 end process;
202
203
204 ------------------------------------------------------------------------------
205 axi_lite_master_generate : if use_axi_lite_bfm generate
206 49 axi_lite_master_inst : entity bfm.axi_lite_master
207 generic map (
208 bus_handle => axi_master
209 )
210 port map (
211 clk => clk,
212
213 axi_lite_m2s => axi_lite_m2s,
214 axi_lite_s2m => axi_lite_s2m
215 );
216
217 else generate
218
219
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9674 axi_lite_m2s <= hard_coded_m2s;
220 end generate;
221
222
223 ------------------------------------------------------------------------------
224 axi_lite_slave_gen : for i in axi_read_slave'range generate
225 18 begin
226
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12 axi_lite_slave_inst : entity bfm.axi_lite_slave
227 generic map (
228 axi_read_slave => axi_read_slave(i),
229 axi_write_slave => axi_write_slave(i),
230 data_width => data_width
231 )
232 port map (
233 clk => clk,
234 --
235 axi_lite_read_m2s => axi_lite_m2s_vec(i).read,
236 axi_lite_read_s2m => axi_lite_s2m_vec(i).read,
237 --
238 axi_lite_write_m2s => axi_lite_m2s_vec(i).write,
239 axi_lite_write_s2m => axi_lite_s2m_vec(i).write
240 );
241 end generate;
242
243
244 ------------------------------------------------------------------------------
245 6 dut : entity work.axi_lite_mux
246 generic map (
247 slave_addrs => slave_addrs
248 )
249 port map (
250 clk => clk,
251
252 axi_lite_m2s => axi_lite_m2s,
253 axi_lite_s2m => axi_lite_s2m,
254
255 axi_lite_m2s_vec => axi_lite_m2s_vec,
256 axi_lite_s2m_vec => axi_lite_s2m_vec
257 );
258
259 end architecture;
260