tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_lite_pipeline.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 use vunit_lib.memory_pkg.all;
15 context vunit_lib.vunit_context;
16 context vunit_lib.vc_context;
17
18 library osvvm;
19 use osvvm.RandomPkg.all;
20
21 library bfm;
22
23 use work.axi_pkg.all;
24 use work.axi_lite_pkg.all;
25
26
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20 entity tb_axi_lite_pipeline is
28 generic (
29 2 runner_cfg : string
30 );
31
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802 end entity;
32 138
33 2 architecture tb of tb_axi_lite_pipeline is
34 2
35
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132 constant data_width : integer := 32;
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670 constant addr_width : integer := 24;
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276 constant num_words : integer := 2048;
38 274
39
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814 constant clk_period : time := 7 ns;
40 138
41 2 signal clk : std_logic := '0';
42
43 802 signal master_m2s, slave_m2s : axi_lite_m2s_t := axi_lite_m2s_init;
44 274 signal master_s2m, slave_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
45
46 2 constant axi_lite_master : bus_master_t := new_bus(
47 data_length => data_width,
48 address_length => master_m2s.read.ar.addr'length
49 );
50
51 2 constant memory : memory_t := new_memory;
52 4 constant axi_lite_read_slave, axi_lite_write_slave : axi_slave_t := new_axi_slave(
53 memory => memory,
54 address_fifo_depth => 8,
55 write_response_fifo_depth => 8,
56 address_stall_probability => 0.3,
57 data_stall_probability => 0.3,
58 write_response_stall_probability => 0.3,
59 min_response_latency => 8 * clk_period,
60 max_response_latency => 16 * clk_period,
61 logger => get_logger("axi_lite_slave_slave")
62 );
63
64 begin
65
66 310854 test_runner_watchdog(runner, 1 ms);
67
68
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376398 clk <= not clk after clk_period / 2;
69
70
71 ------------------------------------------------------------------------------
72 2 main : process
73 2 variable rnd : RandomPType;
74 66 variable data : std_logic_vector(data_width - 1 downto 0);
75 2 variable address : integer;
76 10 variable buf : buffer_t;
77 begin
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6 test_runner_setup(runner, runner_cfg);
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4 rnd.InitSeed(rnd'instance_name);
80
81 2 buf := allocate(memory, 4 * num_words);
82
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2 for idx in 0 to num_words - 1 loop
84 4096 address := 4 * idx;
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4096 data := rnd.RandSlv(data'length);
86
87 -- Call is non-blocking. I.e. we will build up a queue of writes.
88
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12288 write_bus(net, axi_lite_master, address, data);
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8192 set_expected_word(memory, address, data);
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20478 wait until rising_edge(clk);
91 end loop;
92
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2 for idx in 0 to num_words - 1 loop
94 4096 address := 4 * idx;
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4096 data := read_word(memory, address, 4);
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24578 check_bus(net, axi_lite_master, address, data);
98 end loop;
99
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45074 test_runner_cleanup(runner);
101 end process;
102
103
104 ------------------------------------------------------------------------------
105 2 axi_lite_master_inst : entity bfm.axi_lite_master
106 generic map (
107 bus_handle => axi_lite_master
108 )
109 port map (
110 clk => clk,
111 --
112 axi_lite_m2s => master_m2s,
113 axi_lite_s2m => master_s2m
114 );
115
116
117 ------------------------------------------------------------------------------
118 2 axi_lite_slave_inst : entity bfm.axi_lite_slave
119 generic map (
120 axi_read_slave => axi_lite_read_slave,
121 axi_write_slave => axi_lite_write_slave,
122 data_width => data_width
123 )
124 port map (
125 clk => clk,
126 --
127 axi_lite_read_m2s => slave_m2s.read,
128 axi_lite_read_s2m => slave_s2m.read,
129 --
130 axi_lite_write_m2s => slave_m2s.write,
131 axi_lite_write_s2m => slave_s2m.write
132 );
133
134
135 ------------------------------------------------------------------------------
136 4 dut : entity work.axi_lite_pipeline
137 generic map (
138 data_width => data_width,
139 addr_width => addr_width
140 )
141 port map (
142 clk => clk,
143 --
144 master_m2s => master_m2s,
145 master_s2m => master_s2m,
146 --
147 slave_m2s => slave_m2s,
148 slave_s2m => slave_s2m
149 );
150
151 end architecture;
152