tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_lite_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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Branches: 67 111 60.4%

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1 24 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16 library osvvm;
17 use osvvm.RandomPkg.all;
18
19 use work.axi_lite_pkg.all;
20
21
22
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4036 entity tb_axi_lite_pkg is
23 generic (
24 data_width : positive;
25 runner_cfg : string
26 );
27 end entity;
28
29 8 architecture tb of tb_axi_lite_pkg is
30 begin
31
32 4 main : process
33
34 20 variable rnd : RandomPType;
35
36 24024 procedure test_slv_conversion(addr_width : positive) is
37 260260 variable data_a : axi_lite_m2s_a_t;
38 292292 variable data_a_slv, data_a_converted : std_logic_vector(axi_lite_m2s_a_sz(addr_width) - 1 downto 0) := (others => '0');
39
40 4004 variable data_w : axi_lite_m2s_w_t := axi_lite_m2s_w_init;
41 436436 variable data_w_slv, data_w_converted : std_logic_vector(axi_lite_m2s_w_sz(data_width) - 1 downto 0);
42
43 4004 variable data_r : axi_lite_s2m_r_t := axi_lite_s2m_r_init;
44 404404 variable data_r_slv, data_r_converted : std_logic_vector(axi_lite_s2m_r_sz(data_width) - 1 downto 0);
45 begin
46 4004 data_w_slv := rnd.RandSLV(data_w_slv'length);
47 4004 data_w := to_axi_lite_m2s_w(data_w_slv, data_width);
48 4004 data_w_converted := to_slv(data_w, data_width);
49
50 8008 check_equal(data_w_converted, data_w_slv, line_num => 50, file_name => "tb_axi_lite_pkg.vhd");
51
52 4004 data_r_slv := rnd.RandSLV(data_r_slv'length);
53 4004 data_r := to_axi_lite_s2m_r(data_r_slv, data_width);
54 4004 data_r_converted := to_slv(data_r, data_width);
55
56 24026 check_equal(data_r_converted, data_r_slv, line_num => 56, file_name => "tb_axi_lite_pkg.vhd");
57 end procedure;
58
59
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8 procedure test_axi_lite_strb is
60
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2 constant got : std_logic_vector(axi_lite_w_strb_sz - 1 downto 0) :=
61 to_axi_lite_strb(data_width);
62
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2 constant expected : positive := 2 ** (data_width / 8) - 1;
63 begin
64
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12062 check_equal(unsigned(got), expected, line_num => 64, file_name => "tb_axi_lite_pkg.vhd");
65 end procedure;
66
67 begin
68
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12 test_runner_setup(runner, runner_cfg);
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8 rnd.InitSeed(rnd'instance_name);
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4 if run("test_slv_conversion") then
72 -- Loop a couple of times to get good random coverage
73 2 for i in 0 to 1000 loop
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4004 test_slv_conversion(addr_width=>32);
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8010 test_slv_conversion(addr_width=>40);
76 end loop;
77
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6 elsif run("test_axi_lite_strb") then
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6 test_axi_lite_strb;
80 end if;
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12054 test_runner_cleanup(runner);
83 end process;
84
85 end architecture;
86