tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 63 63 100.0%
Branches: 93 140 66.4%

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1 96 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16 library osvvm;
17 use osvvm.RandomPkg.all;
18
19 use work.axi_pkg.all;
20
21
22
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8136 entity tb_axi_pkg is
23 generic (
24 data_width : integer;
25 id_width : integer;
26 addr_width : integer;
27 runner_cfg : string
28 );
29 end entity;
30
31 32 architecture tb of tb_axi_pkg is
32 begin
33
34 16 main : process
35 80 variable rnd : RandomPType;
36
37 80080 procedure test_slv_conversion(iteration : natural) is
38 8008 constant offset_max : integer := 73;
39
40 8008 variable data_a : axi_m2s_a_t := axi_m2s_a_init;
41 420420 variable data_a_converted :
42 std_logic_vector(axi_m2s_a_sz(id_width=>id_width, addr_width=>addr_width) - 1 downto 0) :=
43 (others => '0');
44 1005004 variable data_a_slv : std_logic_vector(data_a_converted'high + offset_max downto 0) :=
45 (others => '0');
46
47 8008 variable data_w : axi_m2s_w_t := axi_m2s_w_init;
48 468468 variable data_w_converted :
49 std_logic_vector(axi_m2s_w_sz(data_width=>data_width, id_width=>id_width) - 1 downto 0) :=
50 (others => '0');
51 1053052 variable data_w_slv : std_logic_vector(data_w_converted'high + offset_max downto 0) :=
52 (others => '0');
53
54 8008 variable data_r : axi_s2m_r_t := axi_s2m_r_init;
55 436436 variable data_r_converted :
56 std_logic_vector(axi_s2m_r_sz(data_width=>data_width, id_width=>id_width) - 1 downto 0) :=
57 (others => '0');
58 1021020 variable data_r_slv : std_logic_vector(data_r_converted'high + offset_max downto 0) :=
59 (others => '0');
60
61 8008 variable data_b : axi_s2m_b_t := axi_s2m_b_init;
62 44044 variable data_b_converted : std_logic_vector(axi_s2m_b_sz(id_width=>id_width) - 1 downto 0) :=
63 (others => '0');
64 628628 variable data_b_slv : std_logic_vector(data_b_converted'high + offset_max downto 0) :=
65 (others => '0');
66
67 8008 variable hi, lo : integer := 0;
68 begin
69 -- Slice slv input, to make sure that ranges don't have to be down to 0
70 8008 lo := iteration mod offset_max;
71
72 8008 hi := data_a_converted'high + lo;
73 8008 data_a_slv(hi downto lo) := rnd.RandSLV(data_a_converted'length);
74 8008 data_a := to_axi_m2s_a(data_a_slv(hi downto lo), id_width=>id_width, addr_width=>addr_width);
75 8008 data_a_converted := to_slv(data_a, id_width=>id_width, addr_width=>addr_width);
76
77 16016 check_equal(data_a_converted, data_a_slv(hi downto lo), line_num => 77, file_name => "tb_axi_pkg.vhd");
78
79 8008 hi := data_w_converted'high + lo;
80 8008 data_w_slv(hi downto lo) := rnd.RandSLV(data_w_converted'length);
81 8008 data_w := to_axi_m2s_w(data_w_slv(hi downto lo), data_width=>data_width, id_width=>id_width);
82 8008 data_w_converted := to_slv(data_w, data_width=>data_width, id_width=>id_width);
83
84 16016 check_equal(data_w_converted, data_w_slv(hi downto lo), line_num => 84, file_name => "tb_axi_pkg.vhd");
85
86 8008 hi := data_r_converted'high + lo;
87 8008 data_r_slv(hi downto lo) := rnd.RandSLV(data_r_converted'length);
88 8008 data_r := to_axi_s2m_r(data_r_slv(hi downto lo), data_width=>data_width, id_width=>id_width);
89 8008 data_r_converted := to_slv(data_r, data_width=>data_width, id_width=>id_width);
90
91 16016 check_equal(data_r_converted, data_r_slv(hi downto lo), line_num => 91, file_name => "tb_axi_pkg.vhd");
92
93 8008 hi := data_b_converted'high + lo;
94 8008 data_b_slv(hi downto lo) := rnd.RandSLV(data_b_converted'length);
95 8008 data_b := to_axi_s2m_b(data_b_slv(hi downto lo), id_width=>id_width);
96 8008 data_b_converted := to_slv(data_b, id_width=>id_width);
97
98 80088 check_equal(data_b_converted, data_b_slv(hi downto lo), line_num => 98, file_name => "tb_axi_pkg.vhd");
99 end procedure;
100
101
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32056 procedure test_combine_response is
102
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72 variable resp, resp1, resp2, expected : std_logic_vector(axi_resp_sz - 1 downto 0);
103 begin
104
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8 for i in 0 to 1000 loop
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8008 resp1 := rnd.RandSlv(resp'length);
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8008 resp2 := rnd.RandSlv(resp'length);
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8008 resp := combine_response(resp1, resp2);
108
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14048 if resp1 = axi_resp_decerr or resp2 = axi_resp_decerr then
110 3480 expected := axi_resp_decerr;
111
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7568 elsif resp1 = axi_resp_slverr or resp2 = axi_resp_slverr then
112 2472 expected := axi_resp_slverr;
113
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3064 elsif resp1 = axi_resp_okay or resp2 = axi_resp_okay then
114 1528 expected := axi_resp_okay;
115 else
116 528 expected := axi_resp_exokay;
117 end if;
118
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64256 check_equal(resp, expected, "resp1: " & to_string(resp1) & ", resp2: " & to_string(resp1), line_num => 118, file_name => "tb_axi_pkg.vhd");
119
120 end loop;
121 end procedure;
122
123 begin
124
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48 test_runner_setup(runner, runner_cfg);
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32 rnd.InitSeed(rnd'instance_name);
126
127
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16 if run("test_slv_conversion") then
128
129 8 for iteration in 0 to 1000 loop
130 -- Loop a couple of times to get good random coverage
131
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32040 test_slv_conversion(iteration);
132 end loop;
133
134
135
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24 elsif run("test_combine_response") then
136
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24 test_combine_response;
137 end if;
138
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32200 test_runner_cleanup(runner);
140 end process;
141
142 end architecture;
143