tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_stream_fifo.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 38 38 100.0%
Branches: 102 180 56.7%

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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 use vunit_lib.memory_pkg.all;
15 context vunit_lib.vunit_context;
16 context vunit_lib.vc_context;
17
18 library osvvm;
19 use osvvm.RandomPkg.all;
20
21 use work.axi_stream_pkg.all;
22
23
24
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20 entity tb_axi_stream_fifo is
25 generic (
26 depth : natural;
27 asynchronous : boolean := false;
28 runner_cfg : string
29 );
30 end entity;
31 2
32 architecture tb of tb_axi_stream_fifo is
33 290
34 4 constant data_width : integer := 32;
35 2 constant user_width : integer := 16;
36 578
37 4 constant clk_fast_period : time := 3 ns;
38 2 constant clk_slow_period : time := 7 ns;
39 2
40 2 signal clk_input, clk_output : std_logic := '0';
41
42 578 signal input_m2s, output_m2s : axi_stream_m2s_t := axi_stream_m2s_init;
43 2 signal input_s2m, output_s2m : axi_stream_s2m_t := axi_stream_s2m_init;
44
45 begin
46
47 21 test_runner_watchdog(runner, 1 ms);
48
49 clk_input_gen : if asynchronous generate
50 10 clk_input <= not clk_input after clk_slow_period / 2;
51 17 clk_output <= not clk_output after clk_fast_period / 2;
52 else generate
53 11 clk_input <= not clk_input after clk_fast_period / 2;
54
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60 clk_output <= not clk_output after clk_fast_period / 2;
55 end generate;
56
57 ------------------------------------------------------------------------------
58 2 main : process
59 2 variable rnd : RandomPType;
60 66 variable data : std_logic_vector(data_width - 1 downto 0);
61 138 variable user : std_logic_vector(user_width - 1 downto 0);
62 begin
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6 test_runner_setup(runner, runner_cfg);
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4 rnd.InitSeed(rnd'instance_name);
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2 if run("test_single_transaction") then
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2 data := rnd.RandSlv(data'length);
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2 user := rnd.RandSlv(user'length);
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66 input_m2s.data(data'range) <= data;
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34 input_m2s.user(user'range) <= user;
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2 input_m2s.valid <= '1';
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6 wait until rising_edge(clk_input) and input_s2m.ready = '1';
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2 input_m2s.valid <= '0';
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2 output_s2m.ready <= '1';
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23 wait until rising_edge(clk_output) and output_m2s.valid = '1';
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4 check_equal(output_m2s.data(data'range), data, line_num => 79, file_name => "tb_axi_stream_fifo.vhd");
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6 check_equal(output_m2s.user(user'range), user, line_num => 80, file_name => "tb_axi_stream_fifo.vhd");
81
82 end if;
83
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30 test_runner_cleanup(runner);
85 end process;
86
87 ------------------------------------------------------------------------------
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4 axi_stream_fifo_inst : entity work.axi_stream_fifo
89 generic map (
90 data_width => data_width,
91 user_width => user_width,
92 asynchronous => asynchronous,
93 depth => depth
94 )
95 port map (
96 clk => clk_input,
97 --
98 input_m2s => input_m2s,
99 input_s2m => input_s2m,
100 --
101 output_m2s => output_m2s,
102 output_s2m => output_s2m,
103 --
104 clk_output => clk_output
105 );
106
107 end architecture;
108