tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_stream_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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Branches: 51 89 57.3%

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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16 library osvvm;
17 use osvvm.RandomPkg.all;
18
19 use work.axi_stream_pkg.all;
20
21
22
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6054 entity tb_axi_stream_pkg is
23 generic (
24 data_width : integer;
25 user_width : integer;
26 runner_cfg : string
27 );
28 end entity;
29
30 12 architecture tb of tb_axi_stream_pkg is
31 begin
32
33 6 main : process
34 30 variable rnd : RandomPType;
35
36 24024 procedure test_slv_conversion(iteration : natural) is
37 6006 constant offset_max : integer := 73;
38
39 6006 variable data : axi_stream_m2s_t := axi_stream_m2s_init;
40 324324 variable data_converted : std_logic_vector(
41 axi_stream_m2s_sz(data_width=>data_width, user_width=>user_width) - 1 downto 0) :=
42 (others => '0');
43 762762 variable data_slv : std_logic_vector(data_converted'high + offset_max downto 0) :=
44 (others => '0');
45
46 6006 variable hi, lo : integer := 0;
47 begin
48 -- Slice slv input, to make sure that ranges don't have to be down to 0
49 6006 lo := iteration mod offset_max;
50
51 6006 hi := data_converted'high + lo;
52 6006 data_slv(hi downto lo) := rnd.RandSLV(data_converted'length);
53 6006 data := to_axi_stream_m2s(
54 data_slv(hi downto lo),
55 data_width=>data_width,
56 user_width=>user_width,
57 valid => '1');
58 6006 data_converted := to_slv(data, data_width=>data_width, user_width=>user_width);
59
60
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48108 check_equal(data_converted, data_slv(hi downto lo), line_num => 60, file_name => "tb_axi_stream_pkg.vhd");
61
62 end procedure;
63
64 begin
65
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18 test_runner_setup(runner, runner_cfg);
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12 rnd.InitSeed(rnd'instance_name);
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6 if run("test_slv_conversion") then
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6 for iteration in 0 to 1000 loop
71 -- Loop a couple of times to get good random coverage
72
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24030 test_slv_conversion(iteration);
73 end loop;
74
75 end if;
76
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24084 test_runner_cleanup(runner);
78 end process;
79
80 end architecture;
81