tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_to_axi_lite.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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Branches: 247 317 77.9%

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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 use vunit_lib.memory_pkg.all;
15 context vunit_lib.vunit_context;
16 context vunit_lib.vc_context;
17
18 library osvvm;
19 use osvvm.RandomPkg.all;
20
21 library bfm;
22
23 use work.axi_pkg.all;
24 use work.axi_lite_pkg.all;
25
26
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20 entity tb_axi_to_axi_lite is
28 generic (
29 2 data_width : integer;
30 runner_cfg : string
31
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406 );
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310 end entity;
33 2
34
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1078 architecture tb of tb_axi_to_axi_lite is
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186 signal clk : std_logic := '0';
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268 constant clk_period : time := 10 ns;
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1016 signal axi_m2s : axi_m2s_t;
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372 signal axi_s2m : axi_s2m_t;
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1144 signal axi_lite_m2s : axi_lite_m2s_t;
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860 signal axi_lite_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
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804 constant memory : memory_t := new_memory;
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140 constant axi_read_slave, axi_write_slave : axi_slave_t := new_axi_slave(
46 memory => memory,
47 address_fifo_depth => 8,
48 write_response_fifo_depth => 8,
49 address_stall_probability => 0.3,
50 data_stall_probability => 0.3,
51 write_response_stall_probability => 0.3,
52 min_response_latency => 8 * clk_period,
53 max_response_latency => 16 * clk_period,
54 logger => get_logger("axi_slave")
55 );
56 4 constant axi_master : bus_master_t := new_bus(
57 data_length => data_width,
58 address_length => axi_m2s.read.ar.addr'length
59 );
60
61 begin
62
63 136922 test_runner_watchdog(runner, 10 ms);
64
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160938 clk <= not clk after clk_period / 2;
65
66
67 ------------------------------------------------------------------------------
68 2 main : process
69 2 variable rnd : RandomPType;
70 194 variable data, got : std_logic_vector(data_width - 1 downto 0);
71 2 constant num_words : integer := 1000;
72 2 constant bytes_per_word : integer := data_width / 8;
73 2 variable address : integer;
74 10 variable buf : buffer_t;
75 begin
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6 test_runner_setup(runner, runner_cfg);
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4 rnd.InitSeed(rnd'instance_name);
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2 buf := allocate(memory, num_words * bytes_per_word);
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2 if run("read_write_data") then
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2 for i in 0 to num_words - 1 loop
82 2000 address := i * bytes_per_word;
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2000 data := rnd.RandSLV(data'length);
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4000 set_expected_word(memory, address, data);
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4002 write_bus(net, axi_master, address, data);
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8000 read_bus(net, axi_master, address, got);
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8002 check_equal(got, data, line_num => 87, file_name => "tb_axi_to_axi_lite.vhd");
88 end loop;
89 end if;
90
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4 check_expected_was_written(memory);
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20024 test_runner_cleanup(runner);
93 end process;
94
95
96 ------------------------------------------------------------------------------
97 2 axi_master_inst : entity bfm.axi_master
98 generic map (
99 bus_handle => axi_master
100 )
101 port map (
102 clk => clk,
103
104 axi_read_m2s => axi_m2s.read,
105 axi_read_s2m => axi_s2m.read,
106
107 axi_write_m2s => axi_m2s.write,
108 axi_write_s2m => axi_s2m.write
109 );
110
111
112 ------------------------------------------------------------------------------
113 2 axi_lite_slave_inst : entity bfm.axi_lite_slave
114 generic map (
115 axi_read_slave => axi_read_slave,
116 axi_write_slave => axi_write_slave,
117 data_width => data_width
118 )
119 port map (
120 clk => clk,
121 --
122 axi_lite_read_m2s => axi_lite_m2s.read,
123 axi_lite_read_s2m => axi_lite_s2m.read,
124 --
125 axi_lite_write_m2s => axi_lite_m2s.write,
126 axi_lite_write_s2m => axi_lite_s2m.write
127 );
128
129
130 ------------------------------------------------------------------------------
131 4 dut : entity work.axi_to_axi_lite
132 generic map (
133 data_width => data_width
134 )
135 port map (
136 clk => clk,
137
138 axi_m2s => axi_m2s,
139 axi_s2m => axi_s2m,
140
141 axi_lite_m2s => axi_lite_m2s,
142 axi_lite_s2m => axi_lite_s2m
143 );
144
145 end architecture;
146