tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/tb_axi_to_axi_lite_vec.vhd
Date: 2021-07-25 04:08:32
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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11
12 library vunit_lib;
13 context vunit_lib.vunit_context;
14 context vunit_lib.com_context;
15 context vunit_lib.vc_context;
16
17 library common;
18 use common.addr_pkg.all;
19
20 library reg_file;
21 use reg_file.reg_file_pkg.all;
22 use reg_file.reg_operations_pkg.all;
23
24 library axi;
25 use axi.axi_pkg.all;
26 use axi.axi_lite_pkg.all;
27
28 library bfm;
29
30
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5904 entity tb_axi_to_axi_lite_vec is
32 generic (
33
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3134 pipeline : boolean;
34
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2722 runner_cfg : string
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54 );
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26 end entity;
37 4826
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830 architecture tb of tb_axi_to_axi_lite_vec is
39
40 14 constant axi_lite_slaves : addr_and_mask_vec_t(0 to 6 - 1) := (
41 0 => (addr => x"0000_0000", mask => x"0000_7000"),
42 1 => (addr => x"0000_1000", mask => x"0000_7000"),
43 2 => (addr => x"0000_2000", mask => x"0000_7000"),
44
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804 3 => (addr => x"0000_3000", mask => x"0000_7000"),
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804 4 => (addr => x"0000_4000", mask => x"0000_7000"),
46 5 => (addr => x"0000_5000", mask => x"0000_7000")
47
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60 );
48 60
49 2 constant reg_map : reg_definition_vec_t(0 to 2 - 1) := (
50 (idx => 0, reg_type => r_w),
51 (idx => 1, reg_type => r_w)
52 );
53
54 2 constant clk_axi_period : time := 7 ns;
55 2 constant clk_axi_lite_slow_period : time := 3 ns;
56 2 constant clk_axi_lite_fast_period : time := 11 ns;
57
58 -- Two of the slaves have same clock as axi clock. Two have a faster clock
59 -- and two have a slower. Corresponds to the clock assignments further below.
60 14 constant clocks_are_the_same : boolean_vector(axi_lite_slaves'range) :=
61 (0 => true, 1 => true, 2 => false, 3 => false, 4 => false, 5 => false);
62
63 2 signal clk_axi : std_logic := '0';
64 26 signal clk_axi_lite_vec : std_logic_vector(axi_lite_slaves'range) := (others => '0');
65
66 742 signal axi_m2s : axi_m2s_t;
67 362 signal axi_s2m : axi_s2m_t;
68
69 2414 signal axi_lite_m2s_vec : axi_lite_m2s_vec_t(axi_lite_slaves'range);
70 842 signal axi_lite_s2m_vec : axi_lite_s2m_vec_t(axi_lite_slaves'range);
71
72 begin
73
74 10942 clk_axi <= not clk_axi after clk_axi_period / 2;
75 5472 clk_axi_lite_vec(0) <= not clk_axi_lite_vec(0) after clk_axi_period / 2;
76 5472 clk_axi_lite_vec(1) <= not clk_axi_lite_vec(1) after clk_axi_period / 2;
77 12762 clk_axi_lite_vec(2) <= not clk_axi_lite_vec(2) after clk_axi_lite_slow_period / 2;
78 12762 clk_axi_lite_vec(3) <= not clk_axi_lite_vec(3) after clk_axi_lite_slow_period / 2;
79 3483 clk_axi_lite_vec(4) <= not clk_axi_lite_vec(4) after clk_axi_lite_fast_period / 2;
80
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3487 clk_axi_lite_vec(5) <= not clk_axi_lite_vec(5) after clk_axi_lite_fast_period / 2;
81
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1254 test_runner_watchdog(runner, 2 ms);
83
84
85 ------------------------------------------------------------------------------
86 2 main : process
87 2 constant beef : std_logic_vector(32 - 1 downto 0) := x"beef_beef";
88 22 constant dead : std_logic_vector(32 - 1 downto 0) := x"dead_dead";
89 begin
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6 test_runner_setup(runner, runner_cfg);
91
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2 for slave_under_test_idx in axi_lite_slaves'range loop
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12 for slave_idx in axi_lite_slaves'range loop
94 -- Write init value to all
95
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146 write_reg(net, 0, beef, axi_lite_slaves(slave_idx).addr);
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432 check_reg_equal(net, 0, beef, axi_lite_slaves(slave_idx).addr);
97 end loop;
98
99 -- Write special value to one of them
100
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24 write_reg(net, 0, dead, axi_lite_slaves(slave_under_test_idx).addr);
101
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12 for slave_idx in axi_lite_slaves'range loop
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72 if slave_idx = slave_under_test_idx then
104 -- Check special value
105
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60 check_reg_equal(net, 0, dead, axi_lite_slaves(slave_idx).addr);
106 else
107 -- The others should still have old value
108
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468 check_reg_equal(net, 0, beef, axi_lite_slaves(slave_idx).addr);
109 end if;
110 end loop;
111 end loop;
112
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948 test_runner_cleanup(runner);
114 end process;
115
116
117 ------------------------------------------------------------------------------
118 2 axi_master_inst : entity bfm.axi_master
119 generic map (
120 bus_handle => regs_bus_master
121 )
122 port map (
123 clk => clk_axi,
124
125 axi_read_m2s => axi_m2s.read,
126 axi_read_s2m => axi_s2m.read,
127
128 axi_write_m2s => axi_m2s.write,
129 axi_write_s2m => axi_s2m.write
130 );
131
132
133 ------------------------------------------------------------------------------
134 register_maps : for slave in axi_lite_slaves'range generate
135
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820 axi_lite_reg_file_inst : entity reg_file.axi_lite_reg_file
136 generic map (
137 regs => reg_map
138 )
139 port map (
140 clk => clk_axi_lite_vec(slave),
141
142 axi_lite_m2s => axi_lite_m2s_vec(slave),
143 axi_lite_s2m => axi_lite_s2m_vec(slave)
144 );
145 end generate;
146
147
148 ------------------------------------------------------------------------------
149
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4 dut : entity work.axi_to_axi_lite_vec
150 generic map (
151 axi_lite_slaves => axi_lite_slaves,
152 clocks_are_the_same => clocks_are_the_same,
153 pipeline => pipeline,
154 data_width => reg_width
155 )
156 port map (
157 clk_axi => clk_axi,
158 axi_m2s => axi_m2s,
159 axi_s2m => axi_s2m,
160
161 clk_axi_lite_vec => clk_axi_lite_vec,
162 axi_lite_m2s_vec => axi_lite_m2s_vec,
163 axi_lite_s2m_vec => axi_lite_s2m_vec
164 );
165
166 end architecture;
167