tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/tb_clock_counter.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 25 25 100.0%
Branches: 67 108 62.0%

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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.numeric_std.all;
11 use ieee.std_logic_1164.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16 library math;
17 use math.math_pkg.all;
18
19
20
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20 entity tb_clock_counter is
21 generic (
22 reference_clock_rate_mhz : positive;
23 target_clock_rate_mhz : positive;
24 runner_cfg : string
25 );
26 end entity;
27
28 architecture tb of tb_clock_counter is
29
30 2 constant resolution_bits : positive := 10;
31 2 constant max_relation_bits : positive := 8;
32
33 2 signal reference_clock, target_clock : std_logic := '0';
34 74 signal target_tick_count : unsigned(resolution_bits + max_relation_bits - 1 downto 0) :=
35 (others => '0');
36
37 2 constant reference_clock_period : time := (1.0 / real(reference_clock_rate_mhz)) * (1 us);
38 2 constant target_clock_period : time := (1.0 / real(target_clock_rate_mhz)) * (1 us);
39
40 4 constant expected_target_tick_count : real :=
41 2 2.0 ** resolution_bits * real(target_clock_rate_mhz) / real(reference_clock_rate_mhz);
42
43 2 begin
44 110
45 28690 test_runner_watchdog(runner, 1 ms);
46 28678 reference_clock <= not reference_clock after reference_clock_period / 2;
47
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166748 target_clock <= not target_clock after target_clock_period / 2;
48
49
50 ------------------------------------------------------------------------------
51 10 main : process
52 begin
53
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6 test_runner_setup(runner, runner_cfg);
54
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2 if run("test_target_tick_count") then
56 -- For the first 2 ** resolution_bits cycles, the value is zero,
57 -- the next 2 ** resolution_bits cycles, the value is almost correct but a little too low.
58
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2 for wait_cycle in 0 to 2 * 2 ** resolution_bits - 1 loop
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20478 wait until rising_edge(reference_clock);
60 end loop;
61
62 -- In all upcoming cycles however, the value shall be correct.
63
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2 for check_iteration in 0 to 5 * 2 ** resolution_bits loop
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40968 wait until rising_edge(reference_clock);
65
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40970 check_equal(
66 real(to_integer(target_tick_count)),
67 expected_target_tick_count,
68 msg=>"check_iteration=" & to_string(check_iteration),
69 max_diff=>1.0
70 , line_num => 65, file_name => "tb_clock_counter.vhd");
71 end loop;
72 end if;
73
74
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63516 test_runner_cleanup(runner);
75 end process;
76
77
78 ------------------------------------------------------------------------------
79
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4 dut : entity work.clock_counter
80 generic map (
81 resolution_bits => resolution_bits,
82 max_relation_bits => max_relation_bits
83 )
84 port map (
85 target_clock => target_clock,
86 --
87 reference_clock => reference_clock,
88 target_tick_count => target_tick_count
89 );
90
91 end architecture;
92