tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/ddr_buffer/tb_ddr_buffer.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library osvvm;
14 use osvvm.RandomPkg.all;
15
16 library vunit_lib;
17 context vunit_lib.vunit_context;
18 context vunit_lib.vc_context;
19
20 library axi;
21 use axi.axi_pkg.all;
22 use axi.axi_lite_pkg.all;
23
24 2 library bfm;
25
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406 library reg_file;
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310 use reg_file.reg_file_pkg.all;
28 use reg_file.reg_operations_pkg.all;
29
30
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54 use work.ddr_buffer_regs_pkg.all;
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802 use work.ddr_buffer_sim_pkg.all;
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20 entity tb_ddr_buffer is
35 generic (
36 2 runner_cfg : string
37 );
38
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204 end entity;
39 618
40 architecture tb of tb_ddr_buffer is
41 540
42
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108 signal clk : std_logic := '0';
43 204 signal axi_read_m2s : axi_read_m2s_t := axi_read_m2s_init;
44 310 signal axi_read_s2m : axi_read_s2m_t := axi_read_s2m_init;
45
46 540 signal axi_write_m2s : axi_write_m2s_t := axi_write_m2s_init;
47 54 signal axi_write_s2m : axi_write_s2m_t := axi_write_s2m_init;
48
49 402 signal regs_m2s : axi_lite_m2s_t := axi_lite_m2s_init;
50 138 signal regs_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
51
52 2 constant axi_width : integer := 64;
53 2 constant burst_length : integer := 16;
54 2 constant burst_size_bytes : integer := burst_length * axi_width / 8;
55
56 2 constant memory : memory_t := new_memory;
57 4 constant axi_read_slave, axi_write_slave : axi_slave_t := new_axi_slave(
58 address_fifo_depth => 1,
59 memory => memory
60 );
61
62 begin
63
64 286 test_runner_watchdog(runner, 1 ms);
65 274 clk <= not clk after 10 ns;
66
67
68 ------------------------------------------------------------------------------
69 2 main : process
70 10 variable rnd : RandomPType;
71
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25 procedure check_counter(expected : natural) is
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99 variable reg_value : reg_t := (others => '0');
74 begin
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109 read_reg(net, ddr_buffer_status, reg_value);
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104 check_equal(
77 unsigned(reg_value(ddr_buffer_status_counter)),
78 expected
79 , line_num => 76, file_name => "tb_ddr_buffer.vhd");
80 end procedure;
81
82 begin
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6 test_runner_setup(runner, runner_cfg);
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4 rnd.InitSeed(rnd'instance_name);
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2 if run("test_ddr_buffer") then
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5 check_counter(0);
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54 run_ddr_buffer_test(net, memory, rnd);
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4 check_counter(ddr_buffer_addrs_array_length);
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54 run_ddr_buffer_test(net, memory, rnd);
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5 check_counter(2 * ddr_buffer_addrs_array_length);
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3 elsif run("test_version") then
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38 check_reg_equal(net, ddr_buffer_version, ddr_buffer_constant_version);
97
98 end if;
99
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4 check_expected_was_written(memory);
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34 test_runner_cleanup(runner);
102 end process;
103
104
105 ------------------------------------------------------------------------------
106 2 axi_lite_master_inst : entity bfm.axi_lite_master
107 generic map (
108 bus_handle => regs_bus_master
109 )
110 port map (
111 clk => clk,
112
113 axi_lite_m2s => regs_m2s,
114 axi_lite_s2m => regs_s2m
115 );
116
117
118 ------------------------------------------------------------------------------
119 2 axi_slave_inst : entity bfm.axi_slave
120 generic map (
121 axi_read_slave => axi_read_slave,
122 axi_write_slave => axi_write_slave,
123 data_width => axi_width
124 )
125 port map (
126 clk => clk,
127
128 axi_read_m2s => axi_read_m2s,
129 axi_read_s2m => axi_read_s2m,
130
131 axi_write_m2s => axi_write_m2s,
132 axi_write_s2m => axi_write_s2m
133 );
134
135
136 ------------------------------------------------------------------------------
137 4 dut : entity work.ddr_buffer_top
138 port map (
139 clk => clk,
140
141 axi_read_m2s => axi_read_m2s,
142 axi_read_s2m => axi_read_s2m,
143
144 axi_write_m2s => axi_write_m2s,
145 axi_write_s2m => axi_write_s2m,
146
147 regs_m2s => regs_m2s,
148 regs_s2m => regs_s2m
149 );
150
151 end architecture;
152