tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/tb_debounce.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 18 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11
12 library vunit_lib;
13 context vunit_lib.vunit_context;
14
15 use work.types_pkg.all;
16
17
18
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30 entity tb_debounce is
19 generic (
20 runner_cfg : string
21 );
22 end entity;
23
24 architecture tb of tb_debounce is
25
26 3 signal clk : std_logic := '0';
27 3 constant clk_period : time := 10 ns;
28
29 6 constant stable_count : positive := 100;
30 3 signal noisy_input, stable_result : std_logic := '0';
31 3
32 9 signal num_rising_edges, num_falling_edges : natural := 0;
33
34 begin
35
36 7581 test_runner_watchdog(runner, 100 us);
37 7563 clk <= not clk after clk_period / 2;
38
39
40 ------------------------------------------------------------------------------
41 15 main : process
42
43
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18993 procedure wait_clk_cycles(count : natural) is
44 begin
45
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32 for wait_cycle in 1 to count loop
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18993 wait until rising_edge(clk);
47 end loop;
48 end procedure;
49
50
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6482 procedure toggle(intervals : integer_vector) is
51 begin
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3 for sequence_idx in intervals'range loop
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6415 wait_clk_cycles(intervals(sequence_idx));
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7730 noisy_input <= not noisy_input;
55 end loop;
56 end procedure;
57
58 begin
59
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9 test_runner_setup(runner, runner_cfg);
60
61 -- All these test are based on a stable_count of 100.
62
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3 if run("test_low_with_noise") then
64 -- Keep low for a bit, then a lot of noise (slightly shorter than stable limit).
65
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2183 toggle((200, 99, 99, 99, 99, 99, 99, 99, 99, 99));
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402 wait_clk_cycles(2 * stable_count);
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2 check_equal(num_rising_edges, 0, line_num => 67, file_name => "tb_debounce.vhd");
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3 check_equal(num_falling_edges, 0, line_num => 68, file_name => "tb_debounce.vhd");
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2 elsif run("test_high_with_noise") then
71 -- Keep low for a bit, then a high period (slightly longer than stable limit),
72 -- then a lot of noise
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1989 toggle((200, 101, 99, 99, 99, 99, 99, 99, 99));
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402 wait_clk_cycles(2 * stable_count);
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2 check_equal(num_rising_edges, 1, line_num => 75, file_name => "tb_debounce.vhd");
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3 check_equal(num_falling_edges, 0, line_num => 76, file_name => "tb_debounce.vhd");
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4 elsif run("test_high_and_low_amongst_noise") then
79 -- Keep low for a bit, then a high period, then some noise, then a high period,
80 -- then some noise.
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2191 toggle((200, 101, 99, 99, 99, 99, 101, 99, 99, 99));
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402 wait_clk_cycles(2 * stable_count);
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2 check_equal(num_rising_edges, 1, line_num => 83, file_name => "tb_debounce.vhd");
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3 check_equal(num_falling_edges, 1, line_num => 84, file_name => "tb_debounce.vhd");
85 end if;
86
87
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15165 test_runner_cleanup(runner);
88 end process;
89
90
91 ------------------------------------------------------------------------------
92 3 counters : process
93 3 variable stable_result_p1 : std_logic := '0';
94 begin
95
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15120 wait until rising_edge(clk);
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3780 num_rising_edges <= num_rising_edges + to_int(stable_result = '1' and stable_result_p1 = '0');
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3780 num_falling_edges <= num_falling_edges + to_int(stable_result = '0' and stable_result_p1 = '1');
99
100 7560 stable_result_p1 := stable_result;
101 end process;
102
103
104 ------------------------------------------------------------------------------
105 6 dut : entity work.debounce
106 generic map (
107 stable_count => stable_count
108 )
109 port map (
110 noisy_input => noisy_input,
111 --
112 clk => clk,
113 stable_result => stable_result
114 );
115
116 end architecture;
117