tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/tb_handshake_splitter.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 68 68 100.0%
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1 6 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11
12 library vunit_lib;
13 context vunit_lib.vunit_context;
14 context vunit_lib.vc_context;
15
16 library osvvm;
17 use osvvm.RandomPkg.all;
18
19 1 use work.types_pkg.all;
20
21
22
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12 entity tb_handshake_splitter is
23 generic (
24 3 runner_cfg : string
25
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19 );
26 2 end entity;
27 6
28
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7 architecture tb of tb_handshake_splitter is
29 2
30
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4 signal clk : std_logic := '0';
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4 constant clk_period : time := 10 ns;
32 1
33
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34 signal input_data : std_logic_vector(8 - 1 downto 0);
34 2 signal input_ready, input_valid : std_logic := '0';
35
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4 signal output0_ready, output0_valid, output1_ready, output1_valid : std_logic := '0';
36 3
37
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2 constant num_words : integer := 2_000;
38 1
39
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2 constant axi_stream_master : axi_stream_master_t := new_axi_stream_master(
40 data_length => input_data'length,
41 protocol_checker => new_axi_stream_protocol_checker(
42 logger => get_logger("axi_stream_master"), data_length => input_data'length));
43
44 1 signal data_check0_done, data_check1_done : boolean := false;
45
46 1 shared variable rnd : RandomPType;
47 1 signal data_queue0 : queue_t := new_queue;
48 2 signal data_queue1 : queue_t := new_queue;
49
50 begin
51
52 9751 test_runner_watchdog(runner, 1 ms);
53
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25761 clk <= not clk after clk_period / 2;
54
55
56 ------------------------------------------------------------------------------
57 1 main : process
58 9 variable data : std_logic_vector(input_data'range) := (others => '0');
59 5 variable last_dummy : std_logic := '1';
60 begin
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3 test_runner_setup(runner, runner_cfg);
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2 rnd.InitSeed(rnd'instance_name);
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1 if run("test_data") then
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1 for i in 1 to num_words loop
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2000 data := rnd.RandSlv(data'length);
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4001 push_axi_stream(net, axi_stream_master, tdata => data, tlast => last_dummy);
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4000 push(data_queue0, data);
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8001 push(data_queue1, data);
70 end loop;
71 end if;
72
73
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3 wait until data_check0_done and data_check1_done;
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46689 test_runner_cleanup(runner);
76 end process;
77
78
79 ------------------------------------------------------------------------------
80 1 data_check0 : process
81 9 variable data : std_logic_vector(input_data'range) := (others => '0');
82 begin
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2000 output0_ready <= '1';
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12574 wait until (output0_ready and output0_valid) = '1' and rising_edge(clk);
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2000 output0_ready <= '0';
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2000 data := pop(data_queue0);
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4000 check_equal(input_data, data, line_num => 89, file_name => "tb_handshake_splitter.vhd");
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2000 for jitter in 1 to rnd.RandInt(2) loop
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14100 wait until rising_edge(clk);
93 end loop;
94 end loop;
95
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1 assert is_empty(data_queue0);
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1 data_check0_done <= true;
98 18062 wait;
99 end process;
100
101
102 ------------------------------------------------------------------------------
103
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61178 output0_axi_stream_protocol_checker_inst : entity vunit_lib.axi_stream_protocol_checker
104 generic map (
105 protocol_checker => new_axi_stream_protocol_checker(
106 logger => get_logger("output0"), data_length => input_data'length)
107 )
108 port map (
109 aclk => clk,
110 tvalid => output0_valid,
111 tready => output0_ready,
112 tdata => input_data
113 );
114
115
116 ------------------------------------------------------------------------------
117 1 data_check1 : process
118 9 variable data : std_logic_vector(input_data'range) := (others => '0');
119 begin
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4000 output1_ready <= '1';
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25412 wait until (output1_ready and output1_valid) = '1' and rising_edge(clk);
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4000 output1_ready <= '0';
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4000 data := pop(data_queue1);
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8000 check_equal(input_data, data, line_num => 126, file_name => "tb_handshake_splitter.vhd");
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27760 wait until rising_edge(clk);
130 end loop;
131 end loop;
132
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2 assert is_empty(data_queue1);
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2 data_check1_done <= true;
135 35860 wait;
136 end process;
137
138
139 ------------------------------------------------------------------------------
140 1 output1_axi_stream_protocol_checker_inst : entity vunit_lib.axi_stream_protocol_checker
141 generic map (
142 protocol_checker => new_axi_stream_protocol_checker(
143 logger => get_logger("output1"), data_length => input_data'length)
144 )
145 port map (
146 aclk => clk,
147 tvalid => output1_valid,
148 tready => output1_ready,
149 tdata => input_data
150 );
151
152 ------------------------------------------------------------------------------
153 1 axi_stream_master_inst : entity vunit_lib.axi_stream_master
154 generic map(
155 master => axi_stream_master
156 )
157 port map(
158 aclk => clk,
159 tvalid => input_valid,
160 tready => input_ready,
161 tdata => input_data
162 );
163
164
165 ------------------------------------------------------------------------------
166 2 dut : entity work.handshake_splitter
167 port map (
168 clk => clk,
169 --
170 input_ready => input_ready,
171 input_valid => input_valid,
172 --
173 output0_ready => output0_ready,
174 output0_valid => output0_valid,
175 --
176 output1_ready => output1_ready,
177 output1_valid => output1_valid
178 );
179
180 end architecture;
181