tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/reg_file/tb_interrupt_register.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 53 53 100.0%
Branches: 178 244 73.0%

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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11
12 library vunit_lib;
13 context vunit_lib.vunit_context;
14
15 library reg_file;
16 use reg_file.reg_file_pkg.all;
17
18
19
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22 entity tb_interrupt_register is
20 generic (
21
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130 runner_cfg : string
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130 );
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130 end entity;
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194 architecture tb of tb_interrupt_register is
26 2
27 2 signal clk : std_logic := '0';
28
29 514 signal sources, mask, clear, status : reg_t := (others => '0');
30 4 signal trigger : std_logic := '0';
31
32 begin
33
34 42 test_runner_watchdog(runner, 2 ms);
35 30 clk <= not clk after 2 ns;
36
37
38 ------------------------------------------------------------------------------
39 138 main : process
40
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20 procedure wait_one_cycle is
41 begin
42
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20 wait until rising_edge(clk);
43 end procedure;
44
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38 procedure wait_a_while is
46 begin
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18 wait until rising_edge(clk);
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30 wait until rising_edge(clk);
49 end procedure;
50
51
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24 procedure check_status(high_bits : integer_vector) is
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198 variable expected : reg_t := (others => '0');
53 begin
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6 for list_idx in high_bits'range loop
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17 expected(high_bits(list_idx)) := '1';
56 end loop;
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24 check_equal(status, expected, line_num => 57, file_name => "tb_interrupt_register.vhd");
58 end procedure;
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8 procedure check_trigger is
61 begin
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8 check_equal(trigger, '1', line_num => 62, file_name => "tb_interrupt_register.vhd");
63 end procedure;
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16 procedure check_no_trigger is
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132 variable expected : reg_t := (others => '0');
67 begin
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100 check_equal(trigger, '0', line_num => 68, file_name => "tb_interrupt_register.vhd");
69 end procedure;
70 begin
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6 test_runner_setup(runner, runner_cfg);
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130 sources <= (0 => '1', 1 => '1', 2 => '1', others => '0');
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10 wait_a_while;
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4 check_status((0, 1, 2));
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4 check_no_trigger;
77
78 -- Source bit and mask bit being high for (at least) one cycle should trigger
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2 mask(0) <= '1';
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8 wait_one_cycle;
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2 sources(0) <= '0';
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12 wait_a_while;
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4 check_status((0, 1, 2));
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4 check_trigger;
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2 if run("test_clear_register_wipes_trigger") then
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1 clear(0) <= '1';
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4 wait_one_cycle;
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65 clear <= (others => '0');
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4 wait_one_cycle;
91 -- Both status bit and trigger are cleared
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2 check_status((1, 2));
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3 check_no_trigger;
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3 elsif run("test_changing_mask_wipes_trigger") then
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1 mask(0) <= '0';
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6 wait_a_while;
98 -- Trigger is cleared but status remains
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2 check_status((0, 1, 2));
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3 check_no_trigger;
101 end if;
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56 test_runner_cleanup(runner);
104 end process;
105
106
107 ------------------------------------------------------------------------------
108 4 dut : entity work.interrupt_register
109 port map (
110 clk => clk,
111
112 sources => sources,
113 mask => mask,
114 clear => clear,
115
116 status => status,
117 trigger => trigger
118 );
119
120 end architecture;
121