tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/tb_periodic_pulser.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 40 40 100.0%
Branches: 93 151 61.6%

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1 30 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.numeric_std.all;
11 use ieee.std_logic_1164.all;
12
13 library osvvm;
14 use osvvm.RandomPkg.all;
15
16 library vunit_lib;
17 context vunit_lib.vunit_context;
18
19
20
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51838 entity tb_periodic_pulser is
21 generic (
22 period : integer range 2 to integer'high;
23 shift_register_length : positive;
24 runner_cfg : string
25 );
26 end entity;
27
28 architecture tb of tb_periodic_pulser is
29
30 5 signal clk : std_logic := '0';
31 5 signal count_enable : std_logic := '1';
32 5 signal pulse : std_logic := '0';
33 5 signal target_clock : std_logic;
34
35 10 signal start_test, test_done : boolean := false;
36
37 begin
38
39
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51813 clk <= not clk after 5 ns;
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51873 test_runner_watchdog(runner, 1 ms);
42
43
44 ------------------------------------------------------------------------------
45 25 main : process
46 begin
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15 test_runner_setup(runner, runner_cfg);
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15 wait until rising_edge(clk);
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5 start_test <= true;
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51803 wait until rising_edge(clk) and test_done;
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103626 test_runner_cleanup(runner);
55 end process;
56
57
58 ------------------------------------------------------------------------------
59 10 stimuli : process
60 5 variable rnd : RandomPType;
61 5 begin
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35 wait until rising_edge(clk) and start_test;
63 5 loop
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103561 wait until rising_edge(clk);
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207182 count_enable <= rnd.RandSlv(1)(1);
66 end loop;
67 end process;
68
69
70 ------------------------------------------------------------------------------
71 5 check : process
72 5 constant num_pulses_to_check : integer := 3;
73 5 variable tick_count : integer range 0 to period - 1;
74 5 variable num_pulses : integer range 0 to num_pulses_to_check := 0;
75 5 variable expected_pulse : std_logic := '0';
76 begin
77
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103596 wait until rising_edge(clk);
78 25899 expected_pulse := '0';
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25899 if count_enable then
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13171 if tick_count = period - 1 then
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15 tick_count := 0;
82 15 expected_pulse := '1';
83 else
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13156 tick_count := tick_count + 1;
85 end if;
86 end if;
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51798 check_equal(pulse, expected_pulse, "Pulse seen at unexpected time", line_num => 88, file_name => "tb_periodic_pulser.vhd");
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25899 if expected_pulse then
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15 num_pulses := num_pulses + 1;
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15 if num_pulses = num_pulses_to_check then
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103596 test_done <= true;
93 end if;
94 end if;
95 end process;
96
97
98 ------------------------------------------------------------------------------
99
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10 dut : entity work.periodic_pulser
100 generic map (
101 period => period,
102 shift_register_length => shift_register_length)
103 port map (
104 clk => clk,
105 count_enable => count_enable,
106 pulse => pulse
107 );
108
109
110 end architecture;
111