tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/tb_resync_counter.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 31 31 100.0%
Branches: 113 170 66.5%

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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16 library common;
17 use common.types_pkg.all;
18
19
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20 entity tb_resync_counter is
20 generic (
21 runner_cfg : string;
22 pipeline_output : boolean
23 );
24 end entity;
25
26 architecture tb of tb_resync_counter is
27 2 constant clk_in_period : time := 3.3 ns;
28 2 constant clk_out_period : time := 4 ns;
29 2 constant max_resync_time : time :=
30 clk_in_period +
31 2*clk_out_period +
32 to_int(pipeline_output) * clk_out_period;
33
34 2 signal clk_in : std_logic := '1';
35 2 signal clk_out : std_logic := '0';
36 66 signal counter_in, counter_out : unsigned(8 - 1 downto 0) := (others => '0');
37 4 constant counter_max : integer := 2 ** counter_in'length - 1;
38 2 begin
39 18
40 165319 test_runner_watchdog(runner, 10 ms);
41 165307 clk_in <= not clk_in after clk_in_period/2;
42
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136414 clk_out <= not clk_out after clk_out_period/2;
43
44
45 ------------------------------------------------------------------------------
46 26 main : process
47
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20864 procedure apply_and_check(value : integer) is
48 begin
49
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5505 wait until rising_edge(clk_in);
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13824 counter_in <= to_unsigned(value, counter_in'length);
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25850 wait until counter_out'event for max_resync_time;
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6143 wait until rising_edge(clk_out);
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3072 check_equal(counter_out, value, line_num => 53, file_name => "tb_resync_counter.vhd");
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16896 wait until counter_out'event for 40*clk_out_period;
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39324 assert not counter_out'event;
56 end procedure;
57
58 begin
59
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6 test_runner_setup(runner, runner_cfg);
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2 loop_twice_to_wrap_counter : for i in 1 to 2 loop
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4 count_up : for value in 0 to counter_max loop
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9822 apply_and_check(value);
64 end loop;
65 end loop;
66
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2 count_down : for value in counter_max downto 0 loop
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4906 apply_and_check(value);
69 end loop;
70
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6170 test_runner_cleanup(runner);
72 end process;
73
74
75 ------------------------------------------------------------------------------
76
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20 dut : entity work.resync_counter
77 generic map (
78 width => counter_in'length,
79 pipeline_output => pipeline_output)
80 port map (
81 clk_in => clk_in,
82 counter_in => counter_in,
83
84 clk_out => clk_out,
85 counter_out => counter_out);
86
87 end architecture;
88