tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/tb_resync_cycles.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16 library common;
17 use common.types_pkg.all;
18
19
20
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30976 entity tb_resync_cycles is
21 generic (
22 output_clock_is_faster : boolean := false;
23 output_clock_is_slower : boolean := false;
24 active_high : boolean;
25 runner_cfg : string
26 );
27 end entity;
28
29 architecture tb of tb_resync_cycles is
30 6 constant counter_width : integer := 3;
31 6 constant clock_period_fast : time := 2 ns;
32 6 constant clock_period_medium : time := 5 ns;
33 6 constant clock_period_slow : time := 10 ns;
34 6 constant active_level : std_logic := to_sl(active_high);
35
36 function clk_out_period return time is
37 begin
38 30934 if output_clock_is_faster then
39 21130 return clock_period_fast;
40 9804 elsif output_clock_is_slower then
41 1286 return clock_period_slow;
42 6 else
43
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8536 return clock_period_medium;
44 end if;
45 end function;
46
47 6 signal clk_in, clk_out : std_logic := '0';
48 6 signal data_in, data_out : std_logic := not active_level;
49
50 6 signal num_data_out : integer := 0;
51 12 signal reset_reference_counter : boolean := false;
52
53 begin
54
55
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42 test_runner_watchdog(runner, 100 us);
56 19538 clk_in <= not clk_in after clock_period_medium / 2;
57 30934 clk_out <= not clk_out after clk_out_period / 2;
58
59
60 ------------------------------------------------------------------------------
61 30 main : process
62
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38944 procedure test(num_cycles : integer) is
63 80 variable start_time : time;
64 begin
65
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316 wait until rising_edge(clk_out);
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80 reset_reference_counter <= true;
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320 wait until rising_edge(clk_out);
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80 reset_reference_counter <= false;
69
70 80 start_time := now;
71
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80 for i in 1 to num_cycles loop
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17228 wait until rising_edge(clk_in);
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8640 data_in <= active_level;
75 end loop;
76
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320 wait until rising_edge(clk_in);
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80 data_in <= not active_level;
79
80
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16360 wait until rising_edge(clk_out) and
81 ((now - start_time) > ((num_cycles + 5) * clock_period_slow));
82
83
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39290 check_equal(num_data_out, num_cycles, line_num => 83, file_name => "tb_resync_cycles.vhd");
84 end procedure;
85 begin
86
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18 test_runner_setup(runner, runner_cfg);
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18 wait until rising_edge(clk_in);
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6 if output_clock_is_slower then
90 -- The resync may fail only after 2**counter_width input cycles
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2 for test_num in 1 to 10 loop
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858 test(2**counter_width);
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902 test(2**counter_width);
94 end loop;
95 else
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4 for test_num in 1 to 10 loop
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23790 test(100);
98 end loop;
99 end if;
100
101
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62190 test_runner_cleanup(runner);
102 end process;
103
104
105 ------------------------------------------------------------------------------
106 6 output : process
107 begin
108
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61856 wait until rising_edge(clk_out);
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15464 if reset_reference_counter then
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80 num_data_out <= 0;
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15384 elsif data_out = active_level then
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30928 num_data_out <= num_data_out + 1;
113 end if;
114 end process;
115
116
117 ------------------------------------------------------------------------------
118 12 dut : entity work.resync_cycles
119 generic map (
120 counter_width => counter_width,
121 active_level => active_level
122 )
123 port map (
124 clk_in => clk_in,
125 data_in => data_in,
126
127 clk_out => clk_out,
128 data_out => data_out);
129
130 end architecture;
131