tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/tb_resync_pulse.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 37 37 100.0%
Branches: 92 141 65.2%

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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16
17
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60 entity tb_resync_pulse is
18 generic (
19 output_clock_is_faster : boolean := false;
20 output_clock_is_slower : boolean := false;
21 input_pulse_overload : boolean := false;
22 runner_cfg : string
23 );
24 end entity;
25
26 architecture tb of tb_resync_pulse is
27 6 constant clock_period_fast : time := 2 ns;
28 6 constant clock_period_medium : time := 5 ns;
29 6 constant clock_period_slow : time := 10 ns;
30
31 12 constant sleep_between_pulses : time := 10 * clock_period_slow;
32 6
33 6 signal clk_in, clk_out : std_logic := '0';
34 12 signal pulse_in, pulse_out : std_logic;
35 6
36 6 signal num_pulses_out : integer := 0;
37 begin
38
39 27642 test_runner_watchdog(runner, 10 ms);
40 27606 clk_in <= not clk_in after clock_period_medium / 2;
41
42 clock_out_gen : if output_clock_is_faster generate
43 23004 clk_out <= not clk_out after clock_period_fast / 2;
44 elsif output_clock_is_slower generate
45 4606 clk_out <= not clk_out after clock_period_slow / 2;
46 else generate
47 9214 clk_out <= transport clk_in after clock_period_medium / 5;
48 end generate;
49
50
51 ------------------------------------------------------------------------------
52 30 main : process
53
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9294 procedure test_pulse(expected_num_pulses : integer) is
54 begin
55
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2394 wait until rising_edge(clk_in);
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600 pulse_in <= '1';
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2400 wait until rising_edge(clk_in);
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600 pulse_in <= '0';
60
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600 if input_pulse_overload then
62 -- Send another pulse
63
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1200 wait until rising_edge(clk_in);
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300 pulse_in <= '1';
65
66
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1200 wait until rising_edge(clk_in);
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300 pulse_in <= '0';
68 end if;
69
70 600 wait for sleep_between_pulses;
71
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11736 check_equal(num_pulses_out, expected_num_pulses, line_num => 71, file_name => "tb_resync_pulse.vhd");
72 end procedure;
73 begin
74
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18 test_runner_setup(runner, runner_cfg);
75
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6 for i in 1 to 100 loop
77 -- In the case of input_pulse_overload we will send more than one input pulse per call to test_pulse().
78 -- But the input gating will make sure that only one pulse arrives on the output, so expected_num_pulses is still i.
79
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6594 test_pulse(i);
80 end loop;
81
82
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41630 test_runner_cleanup(runner);
83 end process;
84
85
86 ------------------------------------------------------------------------------
87 6 output : process
88 begin
89
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39194 wait until pulse_out = '1' and rising_edge(clk_out);
90
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1200 num_pulses_out <= num_pulses_out + 1;
91 end process;
92
93
94 ------------------------------------------------------------------------------
95 12 dut : entity work.resync_pulse
96 generic map (
97 assert_false_on_pulse_overload => not input_pulse_overload
98 )
99 port map (
100 clk_in => clk_in,
101 pulse_in => pulse_in,
102
103 clk_out => clk_out,
104 pulse_out => pulse_out);
105
106 end architecture;
107