tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/tb_resync_slv_level.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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Branches: 130 192 67.7%

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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16
17
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1110 entity tb_resync_slv_level is
18 generic (
19 test_coherent : boolean;
20 output_clock_is_faster : boolean;
21 enable_input_register : boolean;
22 runner_cfg : string
23 );
24 end entity;
25
26 architecture tb of tb_resync_slv_level is
27
28 6 constant clock_period_fast : time := 2 ns;
29 6 constant clock_period_medium : time := 10 ns;
30 10 constant clock_period_slow : time := 10 ns;
31 68
32 function clk_out_period return time is
33 4 begin
34
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1194 if output_clock_is_faster then
35 550 return clock_period_fast;
36 else
37
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524 return clock_period_slow;
38 end if;
39 end function;
40
41 6 constant one : std_logic_vector(16 - 1 downto 0) := x"1111";
42 6 constant two : std_logic_vector(one'range) := x"2222";
43
44 6 signal clk_in, clk_out : std_logic := '0';
45 198 signal data_in, data_out : std_logic_vector(one'range) := one;
46
47 begin
48
49
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42 test_runner_watchdog(runner, 10 ms);
50 1068 clk_out <= not clk_out after clk_out_period / 2;
51
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662 clk_in <= not clk_in after clock_period_medium / 2;
52
53 2
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66 ------------------------------------------------------------------------------
55 126 main : process
56
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2599 procedure wait_cycles(signal clk : std_logic; num_cycles : in integer) is
58 begin
59
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24 for i in 0 to num_cycles-1 loop
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2599 wait until rising_edge(clk);
61 end loop;
62 end procedure;
63
64
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85 procedure wait_for_input_value_to_propagate is
65 6 variable clk_in_wait_count, clk_out_wait_count : natural := 0;
66 begin
67 -- Wait to assign input value in tb
68 6 clk_in_wait_count := 1;
69 -- Two registers
70 6 clk_out_wait_count := 2;
71
72
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6 if test_coherent then
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2 clk_in_wait_count := clk_in_wait_count + 3;
74 end if;
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6 if enable_input_register then
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2 clk_in_wait_count := clk_in_wait_count + 1;
78 end if;
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37 wait_cycles(clk_in, clk_in_wait_count);
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1213 wait_cycles(clk_out, clk_out_wait_count);
82 end procedure;
83
84 begin
85
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18 test_runner_setup(runner, runner_cfg);
86
87 -- Default value
88
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12 check_equal(data_out, one, line_num => 88, file_name => "tb_resync_slv_level.vhd");
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18 wait until rising_edge(clk_out);
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12 check_equal(data_out, one, line_num => 91, file_name => "tb_resync_slv_level.vhd");
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492 wait_cycles(clk_out, 40);
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12 check_equal(data_out, one, line_num => 94, file_name => "tb_resync_slv_level.vhd");
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102 data_in <= two;
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61 wait_for_input_value_to_propagate;
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12 check_equal(data_out, two, line_num => 98, file_name => "tb_resync_slv_level.vhd");
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492 wait_cycles(clk_out, 40);
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12 check_equal(data_out, two, line_num => 101, file_name => "tb_resync_slv_level.vhd");
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2256 test_runner_cleanup(runner);
104 end process;
105
106
107 ------------------------------------------------------------------------------
108 6 assert_output_always_valid_value : process
109 begin
110
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2124 wait until rising_edge(clk_out);
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1321 assert data_out = one or data_out = two;
112 end process;
113
114
115 ------------------------------------------------------------------------------
116 choose_dut : if test_coherent generate
117
118
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8 dut : entity work.resync_slv_level_coherent
119 generic map (
120 width => data_in'length,
121 default_value => one
122 )
123 port map (
124 clk_in => clk_in,
125 data_in => data_in,
126
127 clk_out => clk_out,
128 data_out => data_out
129 );
130
131 else generate
132
133
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20 dut : entity work.resync_slv_level
134 generic map (
135 width => data_in'length,
136 enable_input_register => enable_input_register,
137 default_value => one
138 )
139 port map (
140 clk_in => clk_in,
141 data_in => data_in,
142
143 clk_out => clk_out,
144 data_out => data_out
145 );
146
147 end generate;
148
149
150 end architecture;
151