tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/resync/tb_resync_slv_level_on_signal.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 32 32 100.0%
Branches: 107 158 67.7%

Line Branch Exec Source
1 6 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15
16
17
27/54
✓ Branch 0 taken 1 times.
✗ Branch 1 not taken.
✓ Branch 3 taken 1 times.
✗ Branch 4 not taken.
✓ Branch 6 taken 1 times.
✗ Branch 7 not taken.
✓ Branch 9 taken 1 times.
✗ Branch 10 not taken.
✓ Branch 12 taken 1 times.
✗ Branch 13 not taken.
✗ Branch 15 not taken.
✓ Branch 16 taken 1 times.
✗ Branch 18 not taken.
✓ Branch 19 taken 1 times.
✓ Branch 21 taken 1 times.
✗ Branch 22 not taken.
✗ Branch 24 not taken.
✓ Branch 25 taken 1 times.
✗ Branch 27 not taken.
✓ Branch 28 taken 1 times.
✓ Branch 30 taken 1 times.
✗ Branch 31 not taken.
✓ Branch 33 taken 1 times.
✗ Branch 34 not taken.
✓ Branch 36 taken 1 times.
✗ Branch 37 not taken.
✓ Branch 39 taken 1 times.
✗ Branch 40 not taken.
✓ Branch 42 taken 1 times.
✗ Branch 43 not taken.
✗ Branch 45 not taken.
✓ Branch 46 taken 1 times.
✗ Branch 48 not taken.
✓ Branch 49 taken 1 times.
✗ Branch 51 not taken.
✓ Branch 52 taken 1 times.
✗ Branch 54 not taken.
✓ Branch 55 taken 1 times.
✓ Branch 57 taken 1 times.
✗ Branch 58 not taken.
✗ Branch 60 not taken.
✓ Branch 61 taken 1 times.
✓ Branch 63 taken 1 times.
✗ Branch 64 not taken.
✓ Branch 66 taken 1 times.
✗ Branch 67 not taken.
✓ Branch 69 taken 1 times.
✗ Branch 70 not taken.
✓ Branch 72 taken 1 times.
✗ Branch 73 not taken.
✓ Branch 75 taken 1 times.
✗ Branch 76 not taken.
✓ Branch 78 taken 1 times.
✗ Branch 79 not taken.
10 entity tb_resync_slv_level_on_signal is
18 generic (
19 runner_cfg : string
20 );
21 end entity;
22
23 architecture tb of tb_resync_slv_level_on_signal is
24 1 signal clk_out : std_logic := '0';
25 65 signal data_in, data_out : std_logic_vector(16-1 downto 0) := (others => '0');
26 2 signal sample_value : std_logic := '0';
27 begin
28
29
3/4
✗ Branch 3 not taken.
✓ Branch 4 taken 1 times.
✓ Branch 6 taken 16 times.
✓ Branch 7 taken 1 times.
24 test_runner_watchdog(runner, 10 ms);
30 167 clk_out <= not clk_out after 2 ns;
31 1
32 1
33
6/8
✓ Branch 4 taken 1 times.
✗ Branch 5 not taken.
✗ Branch 7 not taken.
✓ Branch 8 taken 1 times.
✓ Branch 11 taken 16 times.
✓ Branch 12 taken 1 times.
✓ Branch 13 taken 16 times.
✓ Branch 14 taken 1 times.
33 ------------------------------------------------------------------------------
34 1 main : process
35
7/8
✓ Branch 0 taken 2 times.
✓ Branch 1 taken 80 times.
✓ Branch 2 taken 160 times.
✓ Branch 3 taken 80 times.
✓ Branch 4 taken 80 times.
✓ Branch 5 taken 2 times.
✓ Branch 6 taken 2 times.
✗ Branch 7 not taken.
406 procedure wait_cycles(signal clk : std_logic; num_cycles : in integer) is
36 begin
37
1/2
✓ Branch 0 taken 2 times.
✗ Branch 1 not taken.
2 for i in 0 to num_cycles-1 loop
38
27/30
✓ Branch 0 taken 1 times.
✓ Branch 1 taken 2 times.
✓ Branch 2 taken 1 times.
✓ Branch 3 taken 1 times.
✓ Branch 4 taken 1 times.
✓ Branch 5 taken 1 times.
✓ Branch 6 taken 1 times.
✓ Branch 7 taken 81 times.
✓ Branch 8 taken 1 times.
✓ Branch 9 taken 1 times.
✓ Branch 10 taken 1 times.
✓ Branch 11 taken 2 times.
✓ Branch 12 taken 1 times.
✓ Branch 13 taken 2 times.
✓ Branch 14 taken 1 times.
✓ Branch 15 taken 1 times.
✓ Branch 16 taken 1 times.
✓ Branch 17 taken 81 times.
✓ Branch 18 taken 1 times.
✓ Branch 19 taken 1 times.
✓ Branch 20 taken 1 times.
✓ Branch 21 taken 2 times.
✗ Branch 22 not taken.
✗ Branch 23 not taken.
✗ Branch 27 not taken.
✓ Branch 28 taken 160 times.
✓ Branch 30 taken 80 times.
✓ Branch 31 taken 80 times.
✓ Branch 33 taken 2 times.
✓ Branch 34 taken 78 times.
592 wait until rising_edge(clk);
39 end loop;
40 end procedure;
41 17 constant zero : std_logic_vector(data_in'range) := (others => '0');
42 21 constant value : std_logic_vector(data_in'range) := x"BAAD";
43 begin
44
2/2
✓ Branch 2 taken 1 times.
✓ Branch 3 taken 1 times.
3 test_runner_setup(runner, runner_cfg);
45
46 -- Module functionality is very simple. This is basically a connectivity test.
47
48
2/4
✗ Branch 3 not taken.
✓ Branch 4 taken 1 times.
✓ Branch 6 taken 1 times.
✗ Branch 7 not taken.
3 wait until rising_edge(clk_out);
49
1/2
✗ Branch 4 not taken.
✓ Branch 5 taken 1 times.
2 check_equal(data_out, zero, line_num => 49, file_name => "tb_resync_slv_level_on_signal.vhd");
50
5/6
✓ Branch 0 taken 16 times.
✓ Branch 1 taken 1 times.
✗ Branch 2 not taken.
✓ Branch 3 taken 16 times.
✓ Branch 4 taken 10 times.
✓ Branch 5 taken 6 times.
17 data_in <= value;
51
52
2/2
✓ Branch 2 taken 80 times.
✓ Branch 3 taken 1 times.
82 wait_cycles(clk_out, 40);
53
1/2
✗ Branch 4 not taken.
✓ Branch 5 taken 1 times.
2 check_equal(data_out, zero, line_num => 53, file_name => "tb_resync_slv_level_on_signal.vhd");
54
2/4
✗ Branch 0 not taken.
✓ Branch 1 taken 1 times.
✓ Branch 2 taken 1 times.
✗ Branch 3 not taken.
1 sample_value <= '1';
55
56
3/4
✗ Branch 3 not taken.
✓ Branch 4 taken 2 times.
✓ Branch 6 taken 1 times.
✓ Branch 7 taken 1 times.
4 wait until rising_edge(clk_out);
57
2/4
✗ Branch 0 not taken.
✓ Branch 1 taken 1 times.
✓ Branch 2 taken 1 times.
✗ Branch 3 not taken.
1 sample_value <= '0';
58
5/6
✓ Branch 0 taken 16 times.
✓ Branch 1 taken 1 times.
✗ Branch 2 not taken.
✓ Branch 3 taken 16 times.
✓ Branch 4 taken 10 times.
✓ Branch 5 taken 6 times.
17 data_in <= zero;
59
60
3/4
✗ Branch 3 not taken.
✓ Branch 4 taken 2 times.
✓ Branch 6 taken 1 times.
✓ Branch 7 taken 1 times.
4 wait until rising_edge(clk_out);
61
1/2
✗ Branch 4 not taken.
✓ Branch 5 taken 1 times.
2 check_equal(data_out, value, line_num => 61, file_name => "tb_resync_slv_level_on_signal.vhd");
62
63
2/2
✓ Branch 2 taken 80 times.
✓ Branch 3 taken 1 times.
82 wait_cycles(clk_out, 40);
64
1/2
✗ Branch 4 not taken.
✓ Branch 5 taken 1 times.
2 check_equal(data_out, value, line_num => 64, file_name => "tb_resync_slv_level_on_signal.vhd");
65
66
1/2
✓ Branch 2 taken 1 times.
✗ Branch 3 not taken.
20 test_runner_cleanup(runner);
67 end process;
68
69
70 ------------------------------------------------------------------------------
71
3/4
✗ Branch 3 not taken.
✓ Branch 4 taken 1 times.
✓ Branch 7 taken 16 times.
✓ Branch 8 taken 1 times.
18 dut : entity work.resync_slv_level_on_signal
72 generic map (
73 width => data_in'length
74 )
75 port map (
76 data_in => data_in,
77
78 clk_out => clk_out,
79 sample_value => sample_value,
80 data_out => data_out
81 );
82
83 end architecture;
84