tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/math/tb_unsigned_divider.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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Branches: 159 247 64.4%

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1 108 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 use vunit_lib.random_pkg.all;
15 context vunit_lib.vunit_context;
16 context vunit_lib.data_types_context;
17
18 library osvvm;
19 use osvvm.RandomPkg.all;
20
21
22
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180 entity tb_unsigned_divider is
23 generic (
24 dividend_width : integer;
25 divisor_width : integer;
26 runner_cfg : string
27 );
28 end entity;
29
30 18 architecture tb of tb_unsigned_divider is
31
32 36 signal clk : std_logic := '0';
33 18
34
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150 signal input_ready : std_logic := '0';
35
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150 signal input_valid : std_logic := '0';
36 132 signal dividend : unsigned(dividend_width - 1 downto 0);
37 150 signal divisor : unsigned(divisor_width - 1 downto 0);
38 18
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264 signal result_ready : std_logic := '0';
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232 signal result_valid : std_logic := '0';
41 132 signal quotient : unsigned(dividend'range);
42 134 signal remainder : unsigned(minimum(divisor_width, dividend_width) - 1 downto 0);
43
44 begin
45
46 3046526 test_runner_watchdog(runner, 20 ms);
47 3046418 clk <= not clk after 2 ns;
48
49
50 ------------------------------------------------------------------------------
51 318 main : process
52
53
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4166382 procedure run_test(dividend_tb, divisor_tb : integer) is
54 begin
55
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1363200 dividend <= to_unsigned(dividend_tb, dividend'length);
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1363200 divisor <= to_unsigned(divisor_tb, divisor'length);
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160000 input_valid <= '1';
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799982 wait until (input_ready and input_valid) = '1' and rising_edge(clk);
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160000 input_valid <= '0';
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160000 result_ready <= '1';
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3366400 wait until (result_ready and result_valid) = '1' and rising_edge(clk);
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5447744 result_ready <= '0';
64 end procedure;
65
66 begin
67
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54 test_runner_setup(runner, runner_cfg);
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18 if run("division") then
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9 for dividend_tb in 0 to 2**dividend_width - 1 loop
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1200 for divisor_tb in 1 to 2**divisor_width - 1 loop
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3817543 run_test(dividend_tb, divisor_tb);
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317600 check_equal(quotient, dividend_tb / divisor_tb, to_string(dividend_tb) & "/" & to_string(divisor_tb), line_num => 73, file_name => "tb_unsigned_divider.vhd");
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637609 check_equal(remainder, dividend_tb rem divisor_tb, to_string(dividend_tb) & "/" & to_string(divisor_tb), line_num => 74, file_name => "tb_unsigned_divider.vhd");
75 end loop;
76 end loop;
77
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27 elsif run("divide_by_zero") then
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9 for dividend_tb in 0 to 2**dividend_width - 1 loop
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28839 run_test(dividend_tb, 0);
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4809 check_equal(quotient, 2 ** quotient'length - 1, to_string(dividend_tb) & "/0", line_num => 81, file_name => "tb_unsigned_divider.vhd"); -- Max value (all 1's)
82 -- Remainder is undefined
83 end loop;
84 end if;
85
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1281344 test_runner_cleanup(runner);
87 end process;
88
89
90 ------------------------------------------------------------------------------
91 36 dut : entity work.unsigned_divider
92 generic map (
93 dividend_width => dividend_width,
94 divisor_width => divisor_width
95 )
96 port map (
97 clk => clk,
98
99 input_ready => input_ready,
100 input_valid => input_valid,
101 dividend => dividend,
102 divisor => divisor,
103
104 result_ready => result_ready,
105 result_valid => result_valid,
106 quotient => quotient,
107 remainder => remainder
108 );
109
110 end architecture;
111