tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/artyz7/top_level_sim_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 2 2 100.0%
Branches: 4 8 50.0%

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6 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library vunit_lib;
10 use vunit_lib.bus_master_pkg.all;
11 use vunit_lib.memory_pkg.all;
12
13 library axi;
14 use axi.axi_lite_pkg.all;
15
16 use work.artyz7_top_pkg.all;
17
18
19 package top_level_sim_pkg is
20
21 6 constant axi_memory : memory_t := new_memory;
22
23 end;
24