tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/types_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 41 47 87.2%
Branches: 74 145 51.0%

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26511640 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.numeric_std.all;
11 use ieee.std_logic_1164.all;
12
13
14 package types_pkg is
15
16 type slv_vec_t is array (integer range <>) of std_logic_vector;
17 type unsigned_vec_t is array (integer range <>) of unsigned;
18 type signed_vec_t is array (integer range <>) of signed;
19
20 type natural_vec_t is array (integer range <>) of natural;
21 type positive_vec_t is array (integer range <>) of positive;
22 type boolean_vec_t is array (integer range <>) of boolean;
23
24 function get_maximum(values : positive_vec_t) return positive;
25
26 function to_sl(value : boolean) return std_logic;
27 function to_bool(value : std_logic) return boolean;
28 function to_bool(value : natural) return boolean;
29
30 subtype binary_integer_t is integer range 0 to 1;
31 function to_int(value : boolean) return binary_integer_t;
32 function to_int(value : std_logic) return binary_integer_t;
33
34 function swap_byte_order(data : std_logic_vector) return std_logic_vector;
35 function swap_bit_order(data : std_logic_vector) return std_logic_vector;
36
37 function count_ones(data : std_logic_vector) return natural;
38
39 end package;
40
41 package body types_pkg is
42
43 function get_maximum(values : positive_vec_t) return positive is
44 -- Minimum possible value
45 4 variable result : positive := 1;
46 begin
47
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4 for value_idx in values'range loop
48
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16 result := maximum(result, values(value_idx));
49 end loop;
50
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4 return result;
51 end function;
52
53 function to_sl(value : boolean) return std_logic is
54 begin
55
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15554580 if value then
56 8103870 return '1';
57 end if;
58 7450710 return '0';
59 end function;
60
61 function to_bool(value : std_logic) return boolean is
62 begin
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4 if value = '1' then
64 2 return true;
65
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2 elsif value = '0' then
66 2 return false;
67 end if;
68 assert false report "Can not convert value " & to_string(value) severity failure;
69 return false;
70 end function;
71
72 function to_bool(value : natural) return boolean is
73 begin
74
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4 if value = 1 then
75 2 return true;
76 end if;
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2 if value = 0 then
78 2 return false;
79 end if;
80
81 assert false report "Can not convert this value " & to_string(value) severity failure;
82 return false;
83 end function;
84
85 function to_int(value : boolean) return binary_integer_t is
86 begin
87
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15578 if value then
88 98 return 1;
89 else
90 15480 return 0;
91 end if;
92 end function;
93
94 function to_int(value : std_logic) return binary_integer_t is
95 begin
96
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97 568962 return 1;
98
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99 10318402 return 0;
100 end if;
101
102 assert false report "Can not convert value " & to_string(value) severity warning;
103 return 0;
104 end function;
105
106 function swap_byte_order(data : std_logic_vector) return std_logic_vector is
107
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132 variable result : std_logic_vector(data'range);
108 4 constant num_bytes : integer := data'length / 8;
109 4 variable result_byte_idx : integer;
110 begin
111 -- Swap endianness of the input word.
112 -- I.e., while maintaining the range and vector direction, swap the location of the data bytes.
113
114
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4 assert data'left > data'right report "Only use with descending range" severity failure;
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4 assert data'length mod 8 = 0 report "Must be a whole number of bytes" severity failure;
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4 for input_byte_idx in 0 to num_bytes - 1 loop
118 16 result_byte_idx := num_bytes - 1 - input_byte_idx;
119
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16 result(result'low + result_byte_idx * 8 + 7 downto result'low + result_byte_idx * 8) :=
120 data(data'low + input_byte_idx * 8 + 7 downto data'low + input_byte_idx * 8);
121 end loop;
122
123 4 return result;
124 end function;
125
126 function swap_bit_order(data : std_logic_vector) return std_logic_vector is
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8 constant length : positive := data'length;
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56 variable result : std_logic_vector(data'range);
129 begin
130 -- While maintaining the range and vector direction, swap the location of the data bits.
131
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8 for idx in 0 to length - 1 loop
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48 result(result'low + idx) := data(data'high - idx);
134 end loop;
135
136 8 return result;
137 end function;
138
139 function count_ones(data : std_logic_vector) return natural is
140
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53454 variable result : integer range 0 to data'length := 0;
141 begin
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53454 for bit_idx in data'range loop
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102328 result := result + to_int(data(bit_idx));
144 end loop;
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53774 return result;
146 end function;
147
148 end package body;
149