FPGA build flow
Tsfpga enables a build flow where many builds can be executed in parallel from the same script call.
Any module can set up build projects using its module_*.py.
All project configuration is located in the module, not in any central script.
The build project is represented using a Python class that abstracts all
settings and operations.
Minimal build_fpga.py example
Given that we follow the folder structure, and have and least one module
that sets up build projects, we can utilize a build_fpga.py
like this:
build_fpga.py file.from pathlib import Path
from tsfpga.build_project_list import BuildProjectList
from tsfpga.module import get_modules
modules = get_modules(modules_folder=Path("path/to/my/modules"))
build_path = Path("generated/my_build_projects")
projects = BuildProjectList(modules=modules, project_filters="*")
projects.create_unless_exists(project_paths=build_path, num_parallel_builds=4)
projects.build(project_path=build_path, num_parallel_builds=4, num_threads_per_build=6)
Of course this is incredibly simplified and hard coded, but it does show the interface to the
tsfpga classes.
The BuildProjectList class will work on a list of
build project objects as supplied by the modules.
An example output from this script is shown below. It shows the build projects being launched in parallel, and then finishing at roughly the same time.
[/home/lukas/work/repo/tsfpga]$ python tsfpga/examples/build_fpga.py
Starting artyz7
Output file: /home/lukas/work/repo/tsfpga/generated/projects/artyz7/output.txt
Starting artyz7_dummy
Output file: /home/lukas/work/repo/tsfpga/generated/projects/artyz7_dummy/output.txt
pass (pass=1 fail=0 total=2) artyz7_dummy (229.5 seconds)
pass (pass=2 fail=0 total=2) artyz7 (229.8 seconds)
==== Summary ========================
Size of artyz7_dummy after implementation:
{
"Total LUTs": 804,
"Logic LUTs": 746,
"LUTRAMs": 58,
"SRLs": 0,
"FFs": 1596,
"RAMB36": 0,
"RAMB18": 1,
"DSP Blocks": 0
}
pass artyz7_dummy (229.5 seconds)
Size of artyz7 after implementation:
{
"Total LUTs": 804,
"Logic LUTs": 746,
"LUTRAMs": 58,
"SRLs": 0,
"FFs": 1596,
"RAMB36": 0,
"RAMB18": 1,
"DSP Blocks": 0
}
pass artyz7 (229.8 seconds)
=====================================
pass 2 of 2
=====================================
Total time was 459.3 seconds
Elapsed time was 229.8 seconds
=====================================
All passed!
Note that before a project is built a register generation is run, so that the project is built using up-to-date register definitions.
Of course a more realistic build_fpga.py would be a little more verbose.
It would probably feature command line arguments that control the behavior, output paths, etc.
And example of this, which also features release artifact packaging, is available in the
repo.
Example project class creation
This is an example of project creation, using the artyz7 example project from the
repo.
Projects are created by modules using the file module_<module_name>.py, see
folder structure for details.
In tsfpga a top-level module that defines build projects is handled just like any other module.
It can use register generation, set up simulations, etc.
The only difference is that it overrides the BaseModule.get_build_projects() method to return
a list of build project objects.
1# Standard libraries
2from pathlib import Path
3
4# First party libraries
5from tsfpga.constraint import Constraint
6from tsfpga.examples.example_env import get_hdl_modules, get_tsfpga_example_modules
7from tsfpga.examples.vivado.project import TsfpgaExampleVivadoProject
8from tsfpga.module import BaseModule
9
10THIS_FILE = Path(__file__)
11
12
13class Module(BaseModule):
14 def get_build_projects(self):
15 projects = []
16
17 modules = get_hdl_modules() + get_tsfpga_example_modules()
18 part = "xc7z020clg400-1"
19
20 tcl_dir = self.path / "tcl"
21 pinning = Constraint(tcl_dir / "artyz7_pinning.tcl")
22 block_design = tcl_dir / "block_design.tcl"
23
24 projects.append(
25 TsfpgaExampleVivadoProject(
26 name="artyz7",
27 modules=modules,
28 part=part,
29 tcl_sources=[block_design],
30 constraints=[pinning],
31 defined_at=THIS_FILE,
32 )
33 )
34
35 projects.append(
36 TsfpgaExampleVivadoProject(
37 name="artyz7_explore",
38 top="artyz7_top",
39 modules=modules,
40 part=part,
41 tcl_sources=[block_design],
42 constraints=[pinning],
43 impl_explore=True,
44 defined_at=THIS_FILE,
45 )
46 )
47
48 projects.append(
49 TsfpgaExampleVivadoProject(
50 name="artyz7_verilog",
51 top="artyz7_top_verilog",
52 modules=modules,
53 part=part,
54 constraints=[pinning],
55 defined_at=THIS_FILE,
56 )
57 )
58
59 projects.append(
60 TsfpgaExampleVivadoProject(
61 name="artyz7_systemverilog",
62 top="artyz7_top_systemverilog",
63 modules=modules,
64 part=part,
65 constraints=[pinning],
66 defined_at=THIS_FILE,
67 )
68 )
69
70 return projects
There is a lot going on here, so lets go through what happens in get_build_projects().
Line 17: Get modules
Firstly we need to get a list of modules that shall be included in the build project. Source files, IP cores, scoped constraints, etc., from all these modules will be added to the project.
It can be a good idea to filter what modules are included here.
If we have a huge module tree but our project only uses a subset of the modules, we might not want
to slow down Vivado by adding everything.
We might also use primitives and IP cores in some modules that are not available for the
target part.
This filtering of modules can be achieved using the arguments to get_modules().
In this case we use two wrappers, get_hdl_modules() and get_tsfpga_example_modules(),
around the get_modules() function.
They set the correct flags (modules paths, default registers
and library_name_has_lib_suffix).
It is recommended to use functions like these so the arguments don’t have to be repeated in
many places.
Line 20-22: TCL files
This module has a sub-folder tcl which contains pinning and a block design.
The block design, which is added to the VivadoProject as a TCL source is simply
represented using it’s path.
The pinning on the other hand, which is used as a constraint in Vivado, must be represented using
the Constraint class.
Line 24-68: Creating project objects
The sources gathered are then use to create project objects that are appended to the projects
list, which is returned at the end of the method.
First a VivadoProject object is created with the name artyz7.
The modules, part name, TCL sources and constraints are passed to the constructor.
There is also a defined_at argument, which is given the path to the module_artyz7.py file.
This is used to get a useful --list result in our build_fpga.py.
The first project does not have the top argument set, which means it will be inferred from
the provided name.
After the first project, a few other projects are set up with different top levels and
different settings.
This is where we could also set different generics for the projects via the
VivadoProject.__init__() constructor.
Note that all of these projects use a project subclass that inherits VivadoProject.
In this case, the project subclass only adds a few more TCL sources with some further
message severity settings.
But using the project subclass concept we could do some more advanced things, for example
setting up build hooks, as decsribed below.
Pre- and post- build function hooks
The VivadoProject functions pre_build() and
post_build() can be convenient in certain use cases.
They will receive all the arguments that are passed to VivadoProject.build(), such as project
path, output path, etc.
Additional named arguments sent to VivadoProject.build() will also be available in
pre_build() and post_build().
Build result with utilization numbers
The VivadoProject.build() method will return a build_result.BuildResult object
upon completion.
It can be inspected to see if the run passed or failed, and what the resource utilization of the
build is.
Example generated TCL
The TCL files below are generated by the VivadoProject class when calling the
VivadoProject.create() and VivadoProject.build() methods as part of a build flow.