Release notes

Release history and changelog for the tsfpga project.

Unreleased (YYYY-MM-DD)

Changes since previous release

Breaking changes

  • Remove bundling of hdl_modules with PyPI release. This also removes the constants/functions tsfpga.HDL_MODULES_LOCATION, tsfpga.HDL_MODULES_TAG, tsfpga.HDL_MODULES_SHA and tsfpga.module.get_hdl_modules().

  • Remove support for formal flow. It’s still a bit too experimental for us to support.

  • Fail Vivado build if any messages with severity ERROR have been reported after synthesis or implementation.

  • Add mandatory heading_character_2 argument to ModuleDocumentation.get_submodule_rst().


11.0.0 (25 october 2021)

Changes since previous release

Breaking changes

10.0.0 (20 october 2021)

Changes since previous release

Breaking changes

9.0.0 (19 october 2021)

Changes since previous release


  • Add common.handshake_master, common.handshake_slave, common.axi_stream_master and common.axi_stream_slave VHDL BMFs.

  • Add common.keep_remover and common.strobe_on_last VHDL entities.

  • Add “peek read” mode to fifo.fifo.

  • Add ModuleDocumentation class for generating Sphinx RST documentation of a module.

Bug fixes

  • Fix bug where common.width_conversion would set output_last on the wrong beat when downconverting.

  • Fix bug in reg_file.reg_operations_pkg.read_modify_reg_bit.


  • Update so that reg_file.axi_lite_reg_file asserts reg_was_read[i] the exact same cycle as the AXI-Lite R transaction occurs (used to be cycle after).

Breaking changes

  • Add common.width_conversion generic enable_last with default value false (used to be implied value true).

  • Move example scripts from examples to tsfpga/examples. This renames the corresponding python package from examples to tsfpga.examples.

8.0.1 (15 july 2021)

Changes since previous release


  • Fix issues with dependency on GitPython in

8.0.0 (6 july 2021)

Changes since previous release


  • Add resync.resync_slv_level_coherent VHDL entity.

  • Add VivadoIpCoreProject class which is the default vivado_project_class for VivadoIpCores.__init__(). If you use a custom class it is a good idea to inherit from this new class instead of VivadoProject.

  • Add IpCoreFile class to represent IP core files, which adds the possibility of parameterizing IP core creation.


  • Fix bug where Vivado build-time generics dictionary was not copied, which could result in incorrect generic values for parallel builds.

Breaking changes

  • Rename all VHDL files/entities/types/constants with prefix axil_ to have prefix axi_lite_. This is done in order to be more descriptive, and to be consistent with axi_stream components. A search/replace axil_ -> axi_lite_ on all VHDL in your FPGA project should be able to adapt for this.

  • Always call BaseModule.registers_hook() from BaseModule.registers(), even when TOML file does not exists. This means that self._registers might be None when entering BaseModule.registers_hook().

  • Add mandatory generic enable_input_register to resync.resync_level and resync.resync_slv_level VHDL entities. See resync_level.vhd file header for details.

  • Rework testbench helper procedures in reg_file.reg_operations_pkg completely.

    1. Rename bits/bits argument to bit_index/bit_indexes.

    2. Rename expected argument to value.

    3. Add mandatory value/values argument to check_reg_equal_bit/check_reg_equal_bits.

    4. Add optional other_bits_value argument to check_reg_equal_bit/check_reg_equal_bits to control what value the non-designated bits are expected to be (default is zero).

    5. Add mandatory value/values argument to wait_until_reg_equals_bit/wait_until_reg_equals_bits.

    6. Add optional other_bits_value argument to wait_until_reg_equals_bit/wait_until_reg_equals_bits to control what value the non-designated bits are expected to be (default is don’t care).

    7. Add mandatory value/values argument to write_reg_bit/write_reg_bits.

    8. Add optional other_bits_value argument to write_reg_bit/write_reg_bits to control what value is assigned to non-designated bits (default is zero).

    9. Add read_modify_write_reg_bit/read_modify_write_reg_bits which performs a read-modify-write where the designated bits are updated.

7.0.0 (17 may 2021)

Changes since previous release


Breaking changes


  • Switch to using python package tomlkit instead of toml for parsing register TOML files.


  • Fix bug in synchronous FIFO when drop_packet is asserted in same cycle as write_last.

6.0.0 (24 march 2021)

Changes since previous release


  • Add fifo.fifo_wrapper VHDL entity.

  • Add drop_packet support to synchronous and asynchronous FIFOs.

  • Add check for pulse width timing violations after implementation in Vivado build system.

  • Check clock interaction after implementation as well in Vivado build system.

  • Add common.clock_counter VHDL entity.

  • Add bfm.axi_read_slave, bfm.axi_write_slave, bfm.axil_read_slave and bfm.axil_write_slave VHDL entities.

Breaking changes

  • Rename fifo.afifo to fifo.asynchronous_fifo.

  • Rename vivado.project.VivadoNetlistProject constructor argument analyze_clock_interaction to analyze_synthesis_timing.

  • Remove tsfpga.vivado.size_checker.Dsp48Blocks in favor of .vivado.size_checker.DspBlocks.

  • Add a pipelining step to improve timing of axi.axi_read_throttle and axi.axi_write_throttle. This introduces three new generics that must be set.

  • Change bfm.axi_slave and bfm.axil_slave interfaces to require two axi_slave_t generics: axi_read_slave and axi_write_slave.

  • Break axi.axi_simple_crossbar into axi.axi_simple_read_crossbar and axi.axi_simple_write_crossbar.

  • Break axi.axil_simple_crossbar into axi.axil_simple_read_crossbar and axi.axil_simple_write_crossbar.


  • Update timing of fifo.fifo port read_ready to get lower fanout and shorter critical path. The change implies an increased latency from a read transaction until write_ready is raised.

5.0.0 (15 february 2021)

Changes since previous release


  • Add optional clk_in port to resync.resync_level which enables a more deterministic latency constraint.

  • Add support for HTML paragraph breaks in register/bit descriptions. Consecutive newlines will be converted to paragraph breaks.

  • Add support for parallel builds of FPGA projects using the BuildProjectList class.

  • Add support for register constants in TOML file.

  • Add axi.axi_read_throttle and axi.axi_write_throttle VHDL entities.

  • Add BaseModule.pre_build() hook function.

  • Add time saving mechanism to only re-create the register VHDL package when necessary.

  • Add common.debounce VHDL entity.

  • Add reg_was_read port to reg_file.axil_reg_file.

  • Add VivadoProject.pre_create() hook function.

  • Allow Vivado project source files to contain spaces.

  • Add .BaseModule.get_formal_files method used to select what files are included in a formal project.

  • Add files_include and files_avoid arguments to BaseModule.get_synthesis_files(), BaseModule.get_simulation_files() and .BaseModule.get_formal_files.

  • Add full_throughput and allow_poor_input_ready_timing generics to common.handshake_pipeline.

Breaking changes


4.0.1 (25 august 2020)

Changes since previous release


  • Add missing files to pypi release.

4.0.0 (21 august 2020)

Changes since previous release


  • Add automatic size checkers for netlist builds: Build result checkers.

  • Add resync.resync_cycles VHDL entity.

Breaking changes

  • Change address types (in axi.axi_pkg, axi.axil_pkg and common.addr_pkg) to be unsigned rather than std_logic_vector. Do the same for AXI id, addr, len and size.

  • Change register definition file from JSON (regs_<name>.json) to TOML (regs_<name>.toml).

  • Build result, as returned by, is now a build_result.BuildResult object instead of a dict.

  • The hooks VivadoProject.pre_build() and VivadoProject.post_build() must now return True upon success.

  • Rename common.types_pkg.natural_vector to natural_vec_t and common.types_pkg.positive_vector to positive_vec_t.

  • Move Vivado-related Python code from tsfpga package to sub-package tsfpga.vivado. The Python modules are renamed accordingly:

    • tsfpga.vivado_utills -> tsfpga.vivado.common

    • tsfpga.vivado_ip_cores -> tsfpga.vivado.ip_cores

    • tsfpga.vivado_project -> tsfpga.vivado.project

    • tsfpga.vivado_simlib -> tsfpga.vivado.simlib

    • tsfpga.vivado_simlib_commercial -> tsfpga.vivado.simlib_commercial

    • tsfpga.vivado_simlib_ghdl -> tsfpga.vivado.simlib_ghdl

    • tsfpga.vivado_tcl -> tsfpga.vivado.tcl

    • tsfpga.utilization_parser -> tsfpga.vivado.utilization_parser

3.0.0 (25 june 2020)

Changes since previous release


  • Add last flag and packet mode to asynchronous FIFO.

  • Add AXI FIFOs and CDCs.

  • Add class for Vivado netlist builds.

  • Add axi.axil_pipeline VHDL entity.


  • Fix issues where VivadoIpCores would re-compile when not necessary.

Breaking changes

  • Lower axi.axi_pkg.axi_id_sz from 32 to 24.

  • Remove default values from AXI conversion functions in axi_pkg and axil_pkg. The addr_width, data_width and id_width always have to be specified.

  • Change ram_type generic of FIFOs and FIFO wrappers to be of type common.attribute_pkg.ram_style_t instead of string.

2.0.0 (20 may 2020)

Changes since previous release


  • Add support for register arrays in register code generation.

  • Add support for default values in register code generation.

  • Add BaseModule.registers_hook() to make it more convenient to manipulate register information from Python.

  • Add last flag and packet mode to synchronous FIFO.

  • Add common.handshake_splitter VHDL entity.


  • Fix synchronous FIFO signal almost_empty being de-asserted too early when almost_empty_level is zero.

  • Area optimize the synchronous and asynchronous FIFOs.

Breaking changes

  • Change meaning of almost_empty FIFO signal to be “‘1’ if there are almost_empty_level or fewer words available to read”. Used to be “fewer than almost_empty_level”.

  • Change register json definition file name from <name>_regs.json to regs_<name>.json.

  • default_registers passed to BaseModule shall now be a list of hdl_registers.register.Register, instead of a dict.

  • Remove generated register constant <name>_regs_zero. Instead add <name>_regs_init with default values.

  • FPGA build projects shall now be set up with BaseModule.get_build_projects() using module_<name>.py rather than with project_<name>.py. See documentation.

  • Rename FpgaProjectList to BuildProjectList to get a consistent naming.

  • Constructor argument to BuildProjectList shall now be a list of modules rather than a list of modules folders.

  • Interface of resync_counter now uses unsigned vectors rather than integer s.

Internal changes

1.0.1 (29 february 2020)

Changes since previous release


  • Include pylintrc and pycodestylerc in release.

1.0.0 (29 february 2020)

Changes since previous release


Breaking changes

  • Refactor to use pathlib.Path instead of strings to represent file system paths. All paths supplied to tsfpga must now be pathlib.Path objects.

  • Rename HdlFile.filename to HdlFile.path.

  • Adjust axi.axi_to_axil to not allow more than one outstanding transaction.

  • Rename FPGAProjectList to FpgaProjectList.

  • axi.axil_mux now responds with DECERR if no slave matches, instead of timing out.

  • Update interface to vivado simlib API with a factory class. See here.

Internal changes

  • Analyze Vivado build timing using a TCL hook instead of reopening the implemented design.

0.1.4 (1 february 2020)

Changes since previous release

New release to test deploy

0.1.3 (1 february 2020)

Changes since previous release

New release to test deploy

0.1.2 (30 january 2020)

Changes since previous release

New release to test deploy

0.1.1 (30 january 2020)

Changes since previous release

New release to test deploy

0.1.0 (30 january 2020)

Initial release