Release notes

Release history and changelog for the tsfpga project.

Unreleased (YYYY-MM-DD)

Changes since previous release

Added

  • Add resync.resync_slv_level_coherent VHDL entity.

Fixed

  • Fix bug where Vivado build-time generics dictionary was not copied, which could result in incorrect generic values for parallel builds.

Breaking changes

  • Rename all VHDL files/entities/types/constants with prefix axil_ to have prefix axi_lite_. This is done in order to be more descriptive, and to be consistent with axi_stream components. A search/replace axil_ -> axi_lite_ on all VHDL in your FPGA project should be able to adapt for this.

  • Always call BaseModule.registers_hook() from BaseModule.registers(), even when TOML file does not exists. This means that self._registers might be None when entering BaseModule.registers_hook().

  • Add mandatory generic enable_input_register to resync.resync_level and resync.resync_slv_level VHDL entities. See resync_level.vhd file header for details.

7.0.0 (17 may 2021)

Changes since previous release

Added

Breaking changes

Changes

  • Switch to using python package tomlkit instead of toml for parsing register TOML files.

Fixed

  • Fix bug in synchronous FIFO when drop_packet is asserted in same cycle as write_last.

6.0.0 (24 march 2021)

Changes since previous release

Added

  • Add fifo.fifo_wrapper VHDL entity.

  • Add drop_packet support to synchronous and asynchronous FIFOs.

  • Add check for pulse width timing violations after implementation in Vivado build system.

  • Check clock interaction after implementation as well in Vivado build system.

  • Add common.clock_counter VHDL entity.

  • Add bfm.axi_read_slave, bfm.axi_write_slave, bfm.axil_read_slave and bfm.axil_write_slave VHDL entities.

Breaking changes

  • Rename fifo.afifo to fifo.asynchronous_fifo.

  • Rename vivado.project.VivadoNetlistProject constructor argument analyze_clock_interaction to analyze_synthesis_timing.

  • Remove tsfpga.vivado.size_checker.Dsp48Blocks in favor of .vivado.size_checker.DspBlocks.

  • Add a pipelining step to improve timing of axi.axi_read_throttle and axi.axi_write_throttle. This introduces three new generics that must be set.

  • Change bfm.axi_slave and bfm.axil_slave interfaces to require two axi_slave_t generics: axi_read_slave and axi_write_slave.

  • Break axi.axi_simple_crossbar into axi.axi_simple_read_crossbar and axi.axi_simple_write_crossbar.

  • Break axi.axil_simple_crossbar into axi.axil_simple_read_crossbar and axi.axil_simple_write_crossbar.

Changes

  • Update timing of fifo.fifo port read_ready to get lower fanout and shorter critical path. The change implies an increased latency from a read transaction until write_ready is raised.

5.0.0 (15 february 2021)

Changes since previous release

Added

  • Add optional clk_in port to resync.resync_level which enables a more deterministic latency constraint.

  • Add support for HTML paragraph breaks in register/bit descriptions. Consecutive newlines will be converted to paragraph breaks.

  • Add support for parallel builds of FPGA projects using the BuildProjectList class.

  • Add support for register constants in TOML file.

  • Add axi.axi_read_throttle and axi.axi_write_throttle VHDL entities.

  • Add BaseModule.pre_build() hook function.

  • Add time saving mechanism to only re-create the register VHDL package when necessary.

  • Add common.debounce VHDL entity.

  • Add reg_was_read port to reg_file.axil_reg_file.

  • Add VivadoProject.pre_create() hook function.

  • Allow Vivado project source files to contain spaces.

  • Add BaseModule.get_formal_files() method used to select what files are included in a formal project.

  • Add files_include and files_avoid arguments to BaseModule.get_synthesis_files(), BaseModule.get_simulation_files() and BaseModule.get_formal_files().

  • Add full_throughput and allow_poor_input_ready_timing generics to common.handshake_pipeline.

Breaking changes

  • Rename resync.resync_on_signal to resync.resync_level_on_signal and resync.resync_slv_on_signal to resync.resync_slv_level_on_signal. This is more descriptive and follows the naming of the other resync blocks.

  • The generated register HTML page no longer supports markdown flavor of using underscores to annotate. Instead use **double asterisks for bold** and *single asterisks for emphasis*. This change is done to make it easier to refer to other registers/constants/signals who very often have underscores in their name.

  • Rename axi.axi_interconnect to axi.axi_simple_crossbar and axi.axil_interconnect to axi.axil_simple_crossbar. This naming is factual (it is a crossbar, not an interconnect) and more descriptive.

  • Rename RegisterList.create_html_table() to RegisterList.create_html_register_table(). Add RegisterList.create_html_constant_table().

  • Deprecate BaseModule.setup_simulations() in favor of BaseModule.setup_vunit().

  • Rework BuildProjectList class completely. See the class documentation, the minimal usage example and the build.py example in the repo.

  • Change VivadoProject to catch non-zero exit code exception if Vivado call fails. If VivadoProject.create() or VivadoProject.open() fail they will return False. If VivadoProject.build() fails, the returned build_result.BuildResult object will have success set to False.

  • Rename <module>_reg_was_written_t to <module>_reg_was_accessed_t in generated register VHDL package.

  • Add mandatory generic width to resync.resync_slv_level and resync.resync_slv_level_on_signal.

  • Rename BaseModule.add_config to BaseModule.add_vunit_config().

  • Rename types_pkg.swap_bytes to types_pkg.swap_byte_order.

  • Remove VivadoIpCores.vivado_project_sources_directory in favor of VivadoIpCores.project_directory.

  • Change tsfpga.create_vhdl_ls_config.create_configuration() argument ip_core_vivado_project_sources_directory to be ip_core_vivado_project_directory.

Changes

4.0.1 (25 august 2020)

Changes since previous release

Changed

  • Add missing files to pypi release.

4.0.0 (21 august 2020)

Changes since previous release

Added

  • Add automatic size checkers for netlist builds: Build result checkers.

  • Add resync.resync_cycles VHDL entity.

Breaking changes

  • Change address types (in axi.axi_pkg, axi.axil_pkg and common.addr_pkg) to be unsigned rather than std_logic_vector. Do the same for AXI id, addr, len and size.

  • Change register definition file from JSON (regs_<name>.json) to TOML (regs_<name>.toml). See example syntax here.

  • Build result, as returned by VivadoProject.build(), is now a build_result.BuildResult object instead of a dict.

  • The hooks VivadoProject.pre_build() and VivadoProject.post_build() must now return True upon success.

  • Rename common.types_pkg.natural_vector to natural_vec_t and common.types_pkg.positive_vector to positive_vec_t.

  • Move Vivado-related Python code from tsfpga package to sub-package tsfpga.vivado. The Python modules are renamed accordingly:

    • tsfpga.vivado_utills -> tsfpga.vivado.common

    • tsfpga.vivado_ip_cores -> tsfpga.vivado.ip_cores

    • tsfpga.vivado_project -> tsfpga.vivado.project

    • tsfpga.vivado_simlib -> tsfpga.vivado.simlib

    • tsfpga.vivado_simlib_commercial -> tsfpga.vivado.simlib_commercial

    • tsfpga.vivado_simlib_ghdl -> tsfpga.vivado.simlib_ghdl

    • tsfpga.vivado_tcl -> tsfpga.vivado.tcl

    • tsfpga.utilization_parser -> tsfpga.vivado.utilization_parser

3.0.0 (25 june 2020)

Changes since previous release

Added

  • Add last flag and packet mode to asynchronous FIFO.

  • Add AXI FIFOs and CDCs.

  • Add class for Vivado netlist builds.

  • Add axi.axil_pipeline VHDL entity.

Fixes

  • Fix issues where VivadoIpCores would re-compile when not necessary.

Breaking changes

  • Lower axi.axi_pkg.axi_id_sz from 32 to 24.

  • Remove default values from AXI conversion functions in axi_pkg and axil_pkg. The addr_width, data_width and id_width always have to be specified.

  • Change ram_type generic of FIFOs and FIFO wrappers to be of type common.attribute_pkg.ram_style_t instead of string.

2.0.0 (20 may 2020)

Changes since previous release

Added

  • Add support for register arrays in register code generation.

  • Add support for default values in register code generation.

  • Add BaseModule.registers_hook() to make it more convenient to manipulate register information from Python.

  • Add last flag and packet mode to synchronous FIFO.

  • Add common.handshake_splitter VHDL entity.

Fixes

  • Fix synchronous FIFO signal almost_empty being de-asserted too early when almost_empty_level is zero.

  • Area optimize the synchronous and asynchronous FIFOs.

Breaking changes

  • Change meaning of almost_empty FIFO signal to be “‘1’ if there are almost_empty_level or fewer words available to read”. Used to be “fewer than almost_empty_level”.

  • Change register json definition file name from <name>_regs.json to regs_<name>.json.

  • default_registers passed to BaseModule shall now be a list of Register, instead of a dict.

  • Remove generated register constant <name>_regs_zero. Instead add <name>_regs_init with default values.

  • FPGA build projects shall now be set up with BaseModule.get_build_projects() using module_<name>.py rather than with project_<name>.py. See documentation.

  • Rename FpgaProjectList to BuildProjectList to get a consistent naming.

  • Constructor argument to BuildProjectList shall now be a list of modules rather than a list of modules folders.

  • Interface of resync_counter now uses unsigned vectors rather than integer s.

Internal changes

  • Refactor register handling to use only one class RegisterList.

1.0.1 (29 february 2020)

Changes since previous release

Added

  • Include pylintrc and pycodestylerc in release.

1.0.0 (29 february 2020)

Changes since previous release

Added

Breaking changes

  • Refactor to use pathlib.Path instead of strings to represent file system paths. All paths supplied to tsfpga must now be pathlib.Path objects.

  • Rename HdlFile.filename to HdlFile.path.

  • Adjust axi.axi_to_axil to not allow more than one outstanding transaction.

  • Rename FPGAProjectList to FpgaProjectList.

  • axi.axil_mux now responds with DECERR if no slave matches, instead of timing out.

  • Update interface to vivado simlib API with a factory class. See here.

Internal changes

  • Analyze Vivado build timing using a TCL hook instead of reopening the implemented design.

0.1.4 (1 february 2020)

Changes since previous release

New release to test deploy

0.1.3 (1 february 2020)

Changes since previous release

New release to test deploy

0.1.2 (30 january 2020)

Changes since previous release

New release to test deploy

0.1.1 (30 january 2020)

Changes since previous release

New release to test deploy

0.1.0 (30 january 2020)

Initial release