tsfpga.examples package
Submodules
tsfpga.examples.build module
- tsfpga.examples.build.arguments(default_temp_dir=PosixPath('/builds/tsfpga/tsfpga/generated'))
Setup of arguments for the example build flow.
- Parameters
default_temp_dir (pathlib.Path) – Default value for output paths.
- tsfpga.examples.build.collect_artifacts(project, output_path)
Example of a method to collect build artifacts. Will create a zip file with the bitstream, hardware definition (.xsa) and register documentation.
- Parameters
project (
VivadoProject
) – Project object that has been built, and who’s artifacts shall now be collected.output_path (pathlib.Path) – Path to the build output. Artifact zip will be placed here as well.
- tsfpga.examples.build.generate_registers(modules, output_path)
Generate all register artifacts from the given modules.
- Parameters
modules (
ModuleList
) – Registers from these modules will be included.output_path (pathlib.Path) – Register artifacts will be placed here.
- tsfpga.examples.build.main()
Main function for building FPGA projects. If you are setting up a new build flow from scratch, you probably want to copy and modify this function, and reuse the others.
- tsfpga.examples.build.setup_and_run(modules, projects, args)
Setup build projects, and execute as instructed by the arguments.
- Parameters
modules (
ModuleList
) – When running a register generation, registers from these modules will be included.projects (
BuildProjectList
) – These build projects will be built.args – Command line argument namespace.
- Returns
0 if everything passed, otherwise non-zero. Can be used for system exit code.
- Return type
tsfpga.examples.example_env module
Common functions and definitions in the example build environment.
- tsfpga.examples.example_env.get_default_registers()
Default registers for tsfpga examples.
- tsfpga.examples.example_env.get_tsfpga_example_modules(names_include=None, names_avoid=None)
Wrapper of the regular
get_modules()
. call with correct settings for tsfpga example modules. This will include the example tsfpga modules, but not the “real” modules.Arguments will be passed on to
get_modules()
.
tsfpga.examples.simulate module
- tsfpga.examples.simulate.find_git_test_filters(args, repo_root, modules, modules_no_sim=None, **setup_vunit_kwargs)
Construct a VUnit test filter that will run all test cases that are affected by git changes. The current git state is compared to origin/master, and differences are derived. See
GitSimulationSubset
for details.- Parameters
args – Command line argument namespace.
repo_root (pathlib.Path) – Path to the repository root. Git commands will be run here.
modules – Will be passed on to
SimulationProject.add_modules()
.modules_no_sim – Will be passed on to
SimulationProject.add_modules()
.setup_vunit_kwargs – Will be passed on to
SimulationProject.add_modules()
.
- Returns
A list of VUnit test case filters.
- Return type
list(str)
- tsfpga.examples.simulate.main()
Main function for the simulation flow. If you are setting up a new simulation environment you probably want to copy and modify this function. The other functions and classes should be reusable in most cases.
tsfpga.examples.simulation_utils module
- class tsfpga.examples.simulation_utils.SimulationProject(args, enable_preprocessing=False)
Bases:
object
Class for setting up and handling a VUnit simulation project. Should be reusable in most cases.
- __init__(args, enable_preprocessing=False)
Create a VUnit project, configured according to the given arguments.
- Parameters
enable_preprocessing (bool) – If
True
, VUnit location/check preprocessing will be enabled.
- add_modules(args, modules, modules_no_sim=None, **setup_vunit_kwargs)
Add module source files to the VUnit project.
- Parameters
args – Command line argument namespace.
modules (
ModuleList
) – These modules will be included in the simulation project.modules_no_sim (
ModuleList
) – These modules will be included in the simulation project, but their test files will not be added.setup_vunit_kwargs – Further arguments that will be sent to
BaseModule.setup_vunit()
for each module. Note that this is a “kwargs” style argument; any number of named arguments can be sent.
- add_vivado_ip_cores(args, modules, vivado_part_name='xc7z020clg400-1', vivado_ip_core_project_class=None)
Generate IP cores from the modules, unless instructed not to by
args
. When running with a commercial simulator they will be added to the VUnit project.- Parameters
args – Command line argument namespace from
simulate.py
.modules (
ModuleList
) – IP cores from these modules will be included in the simulation project.vivado_part_name (str) – Part name to be used for Vivado IP core project. Might have to change from default depending on what parts you have available in your Vivado installation.
vivado_ip_core_project_class – Class to be used for Vivado IP core project. Can be left at default in most cases.
- Returns
Path to the Vivado IP core project’s
project
directory.- Return type
- add_vivado_simlib(args)
Add Vivado simlib to the VUnit project, unless instructed not to by
args
. Will compile simlib if necessary.- Parameters
args – Command line argument namespace from
simulate.py
.- Returns
The simlib object.
- Return type
- tsfpga.examples.simulation_utils.create_vhdl_ls_configuration(output_path, temp_files_path, modules, ip_core_vivado_project_directory=None)
Create config for vhdl_ls (https://github.com/VHDL-LS/rust_hdl). Granted this might no be the “correct” place for this functionality. But since the call is somewhat quick (~10 ms), and simulate.py is run “often” it seems an appropriate place in order to always have an up-to-date vhdl_ls config.
- Parameters
output_path (pathlib.Path) – Config file will be placed here.
temp_files_path (pathlib.Path) – Some temporary files will be placed here.
modules (
ModuleList
) – These modules will be added.ip_core_vivado_project_directory (pathlib.Path) – Vivado IP core files in this location will be added.
- tsfpga.examples.simulation_utils.get_arguments_cli(default_output_path)
Get arguments for the simulation flow.
- Parameters
default_output_path (pathlib.Path) – Will be set as default for output path arguments (both VUnit files and Vivado files).