tsfpga is a development platform that aims to streamline the code structure and user experience in your FPGA project. With its python build/simulation flow it is perfect for CI/CD and test-driven development. Focus has been placed on flexibility and modularization, achieving scalability even in very large multi-vendor code bases.
Source code centric project structure: Build projects, test configurations, constraints, IP cores, etc. are handled close to the source code.
Automatically adds build/simulation sources if a recognized folder structure is used.
Enables local VUnit configuration setup without multiple
Handling of IP cores and simlib for your simulation project, with automatic re-compile when necessary.
Python-based parallel Vivado build system.
Tightly integrated with hdl_registers. Register code generation will be performed before each simulation and each build.
Released under the very permissive BSD 3-Clause License.
The maintainers place high focus on quality, with everything having good unit test coverage and a thought-out structure. The project is mature and used in many production environments.