tsfpga.examples.vivado package

Submodules

tsfpga.examples.vivado.project module

class tsfpga.examples.vivado.project.TsfpgaExampleVivadoNetlistProject(analyze_synthesis_timing: bool = False, build_result_checkers: list[SizeChecker | MaximumLogicLevel] | None = None, **kwargs: Any)

Bases: VivadoNetlistProject

Example Vivado project class for netlist builds. Shows how to override and extend the base behavior.

pre_create(generics: dict[str, Any], **kwargs: Any) → bool

Override parent method to add custom behavior. Update TCL sources just before project creation.

class tsfpga.examples.vivado.project.TsfpgaExampleVivadoProject(name: str, modules: ModuleList, part: str, top: str | None = None, generics: dict[str, bool | float | StringGenericValue | BitVectorGenericValue] | None = None, constraints: list[Constraint] | None = None, tcl_sources: list[Path] | None = None, build_step_hooks: list[BuildStepTclHook] | None = None, vivado_path: Path | None = None, default_run_index: int = 1, impl_explore: bool = False, defined_at: Path | None = None, **other_arguments: Any)

Bases: VivadoProject

Example Vivado project class. Shows how to override and extend the base behavior.

pre_build(generics: dict[str, Any], **kwargs: Any) → bool

Is called right before the Vivado system call that builds the project. Override parent method to add custom behavior.

Note that this function is called after generating register HDL artifacts in the build flow. Hence, the register constants we set will only be available in the generated software code, not in the HDL. Hence we can run many builds in parallel, without having race conditions between the different values in HDL on the filesystem.

pre_create(generics: dict[str, Any], **kwargs: Any) → bool

Is called right before the Vivado system call that creates the project. Override parent method to add custom behavior.