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Module statements missing excluded coverage
Total 5287 375 0 93%
tsfpga/__init__.py 15 0 0 100%
tsfpga/about.py 6 6 0 0%
tsfpga/build_project_list.py 176 5 0 97%
tsfpga/build_step_tcl_hook.py 10 0 0 100%
tsfpga/constraint.py 15 0 0 100%
tsfpga/create_vhdl_ls_config.py 28 28 0 0%
tsfpga/formal_project.py 111 34 0 69%
tsfpga/git_simulation_subset.py 80 17 0 79%
tsfpga/git_utils.py 42 2 0 95%
tsfpga/hdl_file.py 18 0 0 100%
tsfpga/ip_core_file.py 12 0 0 100%
tsfpga/module.py 115 4 0 97%
tsfpga/module_documentation.py 68 8 0 88%
tsfpga/module_list.py 30 0 0 100%
tsfpga/registers/__init__.py 1 0 0 100%
tsfpga/registers/bit.py 37 0 0 100%
tsfpga/registers/bit_vector.py 52 0 0 100%
tsfpga/registers/constant.py 7 0 0 100%
tsfpga/registers/html_translator.py 30 0 0 100%
tsfpga/registers/parser.py 125 0 0 100%
tsfpga/registers/register.py 53 0 0 100%
tsfpga/registers/register_array.py 27 0 0 100%
tsfpga/registers/register_c_generator.py 92 0 0 100%
tsfpga/registers/register_code_generator.py 20 1 0 95%
tsfpga/registers/register_cpp_generator.py 141 0 0 100%
tsfpga/registers/register_field.py 21 5 0 76%
tsfpga/registers/register_html_generator.py 99 0 0 100%
tsfpga/registers/register_list.py 157 0 0 100%
tsfpga/registers/register_python_generator.py 22 0 0 100%
tsfpga/registers/register_vhdl_generator.py 103 0 0 100%
tsfpga/registers/test/__init__.py 0 0 0 100%
tsfpga/registers/test/conftest.py 1 0 0 100%
tsfpga/registers/test/test_bit.py 37 0 0 100%
tsfpga/registers/test/test_bit_vector.py 54 0 0 100%
tsfpga/registers/test/test_constant.py 6 0 0 100%
tsfpga/registers/test/test_html_translator.py 49 0 0 100%
tsfpga/registers/test/test_parser.py 168 0 0 100%
tsfpga/registers/test/test_register.py 68 0 0 100%
tsfpga/registers/test/test_register_array.py 58 0 0 100%
tsfpga/registers/test/test_register_code_generation.py 46 0 0 100%
tsfpga/registers/test/test_register_html_generator.py 76 0 0 100%
tsfpga/registers/test/test_register_list.py 216 0 0 100%
tsfpga/registers/test/test_register_python_generator.py 9 0 0 100%
tsfpga/registers/test/test_register_vhdl_generator.py 38 0 0 100%
tsfpga/sby_writer.py 30 0 0 100%
tsfpga/svn_utils.py 49 10 0 80%
tsfpga/system_utils.py 61 1 0 98%
tsfpga/test/__init__.py 1 0 0 100%
tsfpga/test/conftest.py 8 0 0 100%
tsfpga/test/functional/__init__.py 0 0 0 100%
tsfpga/test/functional/commercial_simulators/__init__.py 0 0 0 100%
tsfpga/test/functional/commercial_simulators/test_compilation.py 29 29 0 0%
tsfpga/test/functional/gcc/__init__.py 0 0 0 100%
tsfpga/test/functional/gcc/test_register_compilation.py 85 0 0 100%
tsfpga/test/functional/vivado/__init__.py 0 0 0 100%
tsfpga/test/functional/vivado/test_building_vivado_project.py 103 103 0 0%
tsfpga/test/lint/__init__.py 0 0 0 100%
tsfpga/test/lint/test_copyright.py 105 5 0 95%
tsfpga/test/lint/test_file_format.py 86 2 0 98%
tsfpga/test/lint/test_python_lint.py 42 0 0 100%
tsfpga/test/test_utils.py 5 1 0 80%
tsfpga/test/unit/__init__.py 0 0 0 100%
tsfpga/test/unit/test_build_project_list.py 98 0 0 100%
tsfpga/test/unit/test_build_step_tcl_hook.py 7 0 0 100%
tsfpga/test/unit/test_constraint.py 23 0 0 100%
tsfpga/test/unit/test_formal_project.py 51 0 0 100%
tsfpga/test/unit/test_git_simulation_subset.py 57 3 0 95%
tsfpga/test/unit/test_git_utils.py 77 3 0 96%
tsfpga/test/unit/test_hdl_file.py 10 0 0 100%
tsfpga/test/unit/test_ip_core_file.py 12 0 0 100%
tsfpga/test/unit/test_module.py 133 1 0 99%
tsfpga/test/unit/test_module_documentation.py 36 0 0 100%
tsfpga/test/unit/test_module_list.py 56 0 0 100%
tsfpga/test/unit/test_sby_writer.py 29 0 0 100%
tsfpga/test/unit/test_svn_utils.py 25 0 0 100%
tsfpga/test/unit/test_system_utils.py 38 0 0 100%
tsfpga/test/unit/test_vhdl_file_documentation.py 17 0 0 100%
tsfpga/test/unit/test_yosys_project.py 27 0 0 100%
tsfpga/vhdl_file_documentation.py 35 1 0 97%
tsfpga/vivado/__init__.py 0 0 0 100%
tsfpga/vivado/build_result.py 33 1 0 97%
tsfpga/vivado/build_result_checker.py 57 1 0 98%
tsfpga/vivado/common.py 32 13 0 59%
tsfpga/vivado/hierarchical_utilization_parser.py 15 1 0 93%
tsfpga/vivado/ip_cores.py 54 1 0 98%
tsfpga/vivado/logic_level_distribution_parser.py 15 1 0 93%
tsfpga/vivado/project.py 175 27 0 85%
tsfpga/vivado/simlib.py 9 0 0 100%
tsfpga/vivado/simlib_commercial.py 33 4 0 88%
tsfpga/vivado/simlib_common.py 63 11 0 83%
tsfpga/vivado/simlib_ghdl.py 73 39 0 47%
tsfpga/vivado/tcl.py 188 4 0 98%
tsfpga/vivado/test/__init__.py 0 0 0 100%
tsfpga/vivado/test/conftest.py 4 0 0 100%
tsfpga/vivado/test/test_build_result.py 18 0 0 100%
tsfpga/vivado/test/test_build_result_checker.py 36 0 0 100%
tsfpga/vivado/test/test_common.py 20 0 0 100%
tsfpga/vivado/test/test_hierarchical_utilization_parser.py 9 0 0 100%
tsfpga/vivado/test/test_ip_cores.py 87 0 0 100%
tsfpga/vivado/test/test_logic_level_distribution_parser.py 10 0 0 100%
tsfpga/vivado/test/test_project.py 240 0 0 100%
tsfpga/vivado/test/test_simlib.py 86 0 0 100%
tsfpga/vivado/test/test_tcl.py 134 0 0 100%
tsfpga/yosys_project.py 22 3 0 86%

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